I have already played around with the Cortex-M1 reference designs for Xilinx Spartan and Artix boards, can you give an indication of what your maximum target frequency for the processor IP core is? Are the referenced 100 MHz a good design practice or even more a limit?
Hi Nuelle, have you managed to use the Cortex-M1 or M3 DesignStart projects for the arty A35? I'm tring to make them run but I have some problems running the implementation regarding some time limits, and maybe you have done it by just configuring a lower clock frequency.
Yes, I successfully managed to get the Cortex-M1 to run on the Arty board. I also reduced the design to the essentials (no debuggers, less peripheral components) and ported it to my own Spartan 7 board. All timing contraints were met at 100 MHz system clock frequency (Xilinx Spartan 7 and Artix 7 in Speedgrade 1). Above 100 MHz, timing constraints of the minimal system failed.