I am using Cortex-M0 DesignStart Pro. I want to port the Model to FPGA, where I do not need any clock gating or power management. Is there a way to remove the PMU completely?
Good question. This configuration doesn't get much attention in the documentation since the focus is on power optimized ASIC implementations.
Within Cortex-M0, there are some architectural clock gates. You can disable these using the ACG parameter.
There is no need to gate the clocks within the example PMU, so you could update the instances of the cm0_pmu_acg module to tie the AGC parameter low.
What is more important is to maintain the handshake for CDBGPWRUPREQ/CDBGPWRUPACK since the DAP protocol requires that those signals can't be tied off. The simplest option is to just remove the clock gating from the example PMU and the system, but if you want then there is no reason that you can't remove the PMU if you follow the tie-off recommendations in the Integration and Implementation Manual.