Digital design flow (synthesis)

In our product, cortex-m0 is internal digital block
1. After synthesis, inout ports such as P0, P1, will be inferred as tri-state logic(TLAT). Is it ok? or please provide the recommanded method.
2. For scan chain insertion, additional independent input "scan enable" is necessary. However there is no extra pin assgin for it in our design. Please let me know if there is any solution.

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  • I have another question:

    In our design,

    1. reset in generated from POR circuit through a counter.

    2. For scan chain insertion, scan signal "test_en" is set by internal register.

    3. some reset signals to flip-flops are generated by another flip-flop(s).

    The question is : additional independent input "scan_reset" is necessary to apply to all flip-flops. However there is no extra pin assgin for it in our design. Please let me know if there is any solution.

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