In our product, cortex-m0 is internal digital block1. After synthesis, inout ports such as P0, P1, will be inferred as tri-state logic(TLAT). Is it ok? or please provide the recommanded method.2. For scan chain insertion, additional independent input "scan enable" is necessary. However there is no extra pin assgin for it in our design. Please let me know if there is any solution.
The example system design that come with design start expect the GPIO ports (P0, P1, etc) to be at the top level. If you have the subsystem implemented internally, it is best to remove the tristate buffers because present of internal tristate buffers:
- can affect ATPG (automatic Test Pattern Generation) and reduce fault coverage.
- can increase power consumption
- can affect maximum clock frequency
Regarding scan enable, although you don't have more pin at the chip package level, you might be able to have the pin at silicon dice level and tie off the signal at chip package? Otherwise you can multiplex the pin with another input pin, and add a state machine to enable test mode only if a predefined bit pattern is shifted into the logic, and disable scanable if the chip is not in test mode.
No more pin even at silicon dice level (WLCSP package).
"multiplex the pin with another input pin, and add a state machine to enable test mode only if a predefined bit pattern is shifted into the logic, and disable scanable if the chip is not in test mode"
would you please provide a example?
Something like this (assume there are some pins that you don't use very often in functional mode like nTRST)
In your ATPG (e.g. TetraMax) you can define setup sequence to trigger the SCANMODE, which the switch the pin functions from normal to test mode for DFT.