Getting started with the technical discussions

In the last year, hundreds of companies have applied and downloaded the Cortex-M0 DesignStart package and used to prototype their system.

Do you want to discuss about the technical challenges you faced and how you solved it? Or, are you looking for some help from the community? Please post adding the tags DesignStart and Technical Discussion to start the discussion within this Community group!

Here there are some frequently asked DesignStart questions:     

Q: How to prototype using the MPS2 board?

You will need both access to Cortex-M0 DesignStart and the Cortex-M Prototyping System (MPS2).

The FPGA is organized in 3 partitions:

  • Base partition. This consists of the IO pins, PLLs, and clock routing
  • Core partition. This consists of the Cortex-M0 DesignStart core
  • User partition. This consists of the CMSDK and FPGA APB subsystems, plus various peripherals for interfacing to the installed memory and other external interfaces. Only this partition can be modified.

The prototyping system is based on the Altera partial reconfiguration flow. This flow allows users to add the modifiable user partition over a portion of the base image, containing the encrypted core.

The Altera Quartus Prime tool is required to implement the partial reconfiguration block and modify the user partition.

Q: Is debug and trace included?

Debug and trace is included in the encrypted Cortex-M0 processor used in the MPS2 board.

The debug unit is not used in simulation and is therefore not included in the obfuscated RTL included in Cortex-M0 DesignStart deliverable.

Q: How can I recompile the testcode?

DesignStart Cortex-M0 is built uses by default using the ARM Keil MDK. As part of the package, ARM includes a 90 day trial of ARM's Keil MDK-Professional. The license key and instructions on how to download MDK are included within the email granting you access to the DesignStart portal.

Q: I cannot configure the Cortex-M0?

The Cortex-M0 processor in DesignStart is a fixed configuration for evaluation purposes.

The Cortex-M0 available for the commercialisation phase of a design is fully configurable. The full version is available with a simplified fast track license.

Q: I am not reaching the target frequency in my implementation based on the DesignStart IP?

The DesignStart Cortex-M0 is delivered as fully synthesizable, obfuscated RTL. This obfuscated RTL logical functionality is represented by AND and OR functions instead of the original RTL. This means it will not be possible to obtain the full performance with respect to licensing a full Cortex-M0.

The fully configurable version of the Cortex-M0 is available via a simplified fast track license.


Looking forward to receiving more questions soon!