Why do I need an AMBA 5 CHI Memory Controller?

ARM® AMBA® 5 CHI Memory Controllers work in concert with AMBA 5 CHI interconnects to provide controls to optimise data flows between many processors and the DDR memory.  In this blog I am going to tell you a bit more about the work ARM is doing to create a high performance path to memory for systems designed around the new AMBA® 5 CHI specification and recently announced CoreLink™ Cache Coherent Network (CCN) products.

In October 2012 ARM announced the first in a range of new IP products to enable our partners to design more energy efficient network infrastructure and servers.  The first silicon based on some of these IP products is becoming available now.


ARM has recently announced a new interconnect product, the CoreLink CCN-508 which increases the number of coherent cores supported and raises the available system bandwidth by adding more ports for memory controllers.

I thought I’d take this opportunity to elaborate a little more on the importance of the memory controller in these complex, high performance systems.

Access to data stored in memory is critical to the performance of any modern SoC design. The scaling number of cores and increased I/O bandwidth has lead to a step change in Memory Controller requirements from traditional ARM based mobile SoCs.

The new CCN products are configurable to have the option to connect an AMBA 4 AXI Memory Controller, or an AMBA 5 CHI Memory Controller like the CoreLink DMC-520.

DMC-520 is optimised to match to the internal structure and operating frequency of the CCN products. The CoreLink DMC-520 supports 72 bit DDR3, DDR3L and DDR4. The AMBA 5 CHI interface can operate at over 1 GHz, providing a very high rate of transactions to the Memory Controller.  Accepting these transactions as quickly as they arrive frees up resources in the CCN.

The Memory Controller can accept up to 128 transactions and uses an advanced scheduling algorithm to re-order these for maximum bandwidth.  Maximum bandwidth is achieved by reducing read to write turnaround and re-ordering the transactions when in row hits occur.

As the controller strives for maximum bandwidth, it must also take into account the Quality of Service (QoS) requirements programmed by the system designer. The QoS mechanisms are distributed throughout the CCN and Memory Controller, enabling different masters in the system to be assigned different types of behaviour (or QoS contracts). Typically a system will consist of some masters requiring

  • Minimum latency
  • Bounded maximum latency
  • Minimum bandwidth

The CCN and AMBA 5 CHI Memory Controller working in concert, bring system designers a broad range of controls over the operation and behaviour of the high performance system built around this new ARM IP.