Pushing the limits of tomorrow’s technology today: Artisan physical IP for 7nm

ARM Physical IP for TSMC 7nm process technology now available

Gone are the days when FPGAs were used primarily for prototyping. Today, developers can drive quickly and cost-effectively into IoT, embedded vision, cloud computing and other sectors using FPGAs. Xilinx is among the companies that have helped enable this drive in recent years, offering new architectures and products on leading-edge process nodes, including 28nm, 20nm and 16nm.

Each of these nodes can bring with it cost challenges and potential risks that can derail the best engineering intentions. ARM has partnered with Xilinx for four process technology generations to deliver physical IP solutions to speed innovation and minimize cost and risk. The strong partnership continues at 7nm: Xilinx, I am pleased to announce, has licensed the ARM® Artisan® physical IP platform for TSMC 7nm FinFET (7FF) process technology to develop its next generation of All Programmable products.

Cutting complexity to size

ARM Artisan IP for TSMC 7FF technology builds on our success with previous generation FinFET technologies. Foundational physical IP provides the building blocks for a SoC design, creating an interface between the underlying semiconductor process technology and the SoC design itself. A key motivator when developing the platform was to be able to provide all of the benefits of the TSMC 7nm process technology, but abstract away the complexities associated with it for the SoC designer. The ARM Artisan platform not only uses the Front End of Line (FEOL) device to provide compelling performance, but also pays special consideration to the Back End of Line (BEOL). In 7nm technology, this could be the difference between a good SoC and an excellent SoC because unlike previous technology nodes, it’s the BEOL that determines the quality of your performance and results, not just the FEOL device. The unique characteristics of the 7FF process technology meant that we had to invent a new memory development methodology, thus the introduction of memory compilers utilizing a cell based layout.  This new memory architecture provides for more consistent patterns in the memory layout, thereby minimizing variation.  Minimizing variation leads to less design margin and better memory PPA for use in the SoC.

Figure 1: ARM Cell Based Layout minimizes variation due to consistent patterns in the design

As metallization becomes more challenging logic routability is critical, especially at 7nm FinFET, to determining the performance, power, and area (PPA) of your SoC.  Solving routability is not limited to just tackling congestion, you also need to pay special attention to IR (voltage drop) and EM (electromigration).  As the process design rules have gotten tighter going from 16/14nm FinFET to 7nm FinFET, the parasitic electrical properties have made it more challenging and complex to design a power grid.  A good power grid can help you get significantly better performance and save both power and area in SoC designs.  The ARM Artisan Power Grid Architect (PGA) simplifies the development of the power grid; with the knowledge of Artisan logic libraries encapsulated in PGA, the power grid creation is correct-by-construction.  As a result, a knowledgeable SoC designer can create a power grid that meets their needs within a matter of hours, versus the several days and iterations it may have taken previously.

Figure 2.  Layout utilization of design before using PGA and after using PGA – resulting in

10% area reduction and effective utilization rate improvement of 20% 

Our logic library development teams have access to the most advanced ARM Cortex®-A CPUs and GPUs, so we are able to test our logic architectures with real-world RTL and solve problems for our customers well before they experience them. This collaboration between physical IP and CPU architecture teams also enables us to develop special logic cells that improve the architectural performance of the CPU.

The signals processed in the SoC may need to interface with other SoCs in a system. To address this, ARM provides a family of General Purpose I/O (GPIO) that supports multiple voltage levels (3.3V and 1.8V) to meet the requirements of various markets segments. ARM GPIOs are programmable and high-performance with innovative low-power features. Smaller than competitive GPIOs, they also meet, or exceed, industry-standard ESD requirements.

ARM and Xilinx have worked closely for years to push boundaries of innovation with each new process node, and the quality of ARM physical IP and this partnership model are extended throughout the ARM partner ecosystem. ARM continues to invest in advanced technology platforms with a view to providing our partners with world-class design solutions, all the while reducing risk by providing high quality foundation IP. Our mission continues to be adding value to SoC designers by solving the advanced semiconductor technology challenge and accelerating adoption. By developing IP in parallel to the process technology development and running multiple test-chips on pre-production PDK to incorporate silicon feedback, ARM helps partners get a head-start on SoC development and reduce technical risk.

ARM Physical IP Platform for TSMC 7nm is available now for evaluation and licensing. If you want to know more about ARM Physical IP platform for TSMC 7nm, please talk to your ARM partner manager.