Change which CPUs are released from reset on Juno

By default on Juno only a single CPU is released from reset on a cold boot:

• Juno r0: Cortex-A53_0
• Juno r1: Cortex-A57_0
• Juno r2: Cortex-A53_0

This is the primary CPU, i.e. `cpu0' in Linux.

You can change the primary CPU by modifying `/SITE1/HBI0262x/board.txt' on the Juno's mounted MMC card, replacing `x' with the letter corresponding to your revision of the Juno:

• Juno r0: `B'
• Juno r1: `C'
• Juno r2: `D'

Look for a line containing `SCC: 0x0F4'. If the line is not present, add the following to the end of the list:

SCC: 0x0F4 0x00000000

And increment the total number of SCC registers by modifying this line:

TOTALSCCS: 12

The encoding of the `SCC: 0x0F4' register is as follows:

• Bits [15:12] of the encode the index of the primary CPU:
  • 0: Cortex-A53_0 ("LITTLE" cluster core 0)
  • 1: Cortex-A53_1 ("LITTLE" cluster core 1)
  • 2: Cortex-A53_2 ("LITTLE" cluster core 2)
  • 3: Cortex-A53_3 ("LITTLE" cluster core 3)
  • 4: Cortex-A57_0 / Cortex-A72_0 ("big" cluster core 0)
  • 5: Cortex-A57_1 / Cortex-A72_1 ("big" cluster core 1)
• Bits [9:8] are a bit mask for powering on "big" cluster cores
• Bits [7:4] are a bit mask for powering on "LITTLE" cluster cores
• Bit [3] enables the above bit masks (when `=0' the system will perform the default power up)

So a value of `0x00000000' performs the default power up with Cortex-A53_0 as the primary CPU.

Changing the value to `0x00004108' would make Cortex-A57_0 / Cortex-A72_0 (i.e. "big" cluster core 0) the primary CPU. Here setting bit [3] enables the power up bit masks, setting bit [8] powers up "big" cluster core 0, and setting the value of bits [15:12] to 4 makes "big" cluster core 0 the primary CPU.

If running a baremetal application you can release multiple CPUs from reset at once, for example a value of `0x000003F8' will power on all CPUs with Cortex-A53_0 as the primary CPU.

Note that AArch64 Linux expects only a single CPU to reach the kernel entrypoint, with all other CPUs either powered down during boot or spinning outside of the kernel until the primary CPU is ready. The kernel will not boot if multiple CPUs are released from reset and reach the kernel entrypoint. See here for more information.