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thomas_cp

thomas_cp

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  • Not Answered

    Other core's view after writing ICC_SGI1R_EL1 to trigger SGI 0

    • CoreLink System Controllers
    • Interrupt
    14115 views
    5 replies
    Latest over 4 years ago
     by 42Bastian Schick
  • Answered

    What kind of memory barrier should be followed by writes ICC_SGI1R_EL1? 0

    • CoreLink System Controllers
    • Corelink
    • CoreLink GIC-500 Generic Interrupt Controller
    • Interrupt
    14358 views
    5 replies
    Latest over 4 years ago
     by 42Bastian Schick
  • Not Answered

    GIC 3.0's SGI interrupt latency seems much bigger than GIC 2.0 0

    • CoreLink System Controllers
    • CoreLink GIC-400 Generic Interrupt Controller
    • Corelink
    • CoreLink GIC-500 Generic Interrupt Controller
    • Interrupt
    17885 views
    15 replies
    Latest over 4 years ago
     by 42Bastian Schick
  • Suggested Answer

    Why linux set memory as inner shareable in multi-cluster ARMv8 cores? 0

    • Cortex-A53
    • Cortex-A57
    • Cache coherency
    • Armv8-A
    • Cortex-A
    10669 views
    7 replies
    Latest over 5 years ago
     by thomas_cp
  • Answered

    Time cost change hugely on some function routine on RealView Versatile EB with ARM11 MPCore 0

    • versatile
    • ARM11 MPCore
    • Arm11
    • Interrupt
    14359 views
    6 replies
    Latest over 5 years ago
     by thomas_cp