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42Bastian Schick

42Bastian Schick

Questions
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  • Not Answered

    Cortex-R52 SPI interrupt routing to PEs not working 0

    792 views
    3 replies
    Latest over 1 year ago
     by Lukas Rohrwild
  • Answered

    Enable/Disable L2 cache on ARM Cortex-A72 0

    • Cortex-A72
    998 views
    4 replies
    Latest over 1 year ago
     by Chanh
  • Suggested Answer

    Set stack size in linker file for Cortex-A72 0

    1091 views
    6 replies
    Latest over 1 year ago
     by Chanh
  • Not Answered

    question about DAP-LITE 0

    • CoreSight Debug Access Port Lite (DAP-Lite)
    1174 views
    3 replies
    Latest over 1 year ago
     by Dibbert
  • Not Answered

    Set A72 frequency to fixed speed 0

    • Cortex-A72
    • AArch64
    • Armv8-A
    777 views
    3 replies
    Latest over 1 year ago
     by 42Bastian Schick
  • Not Answered

    A description of each of the pipeline stages / ARMv9 Cortex-A510 0

    1169 views
    3 replies
    Latest over 1 year ago
     by 42Bastian Schick
  • Suggested Answer

    force the toolchain to only use Thumb-16 in M0/3/4 0

    • GCC
    • Compilers
    • Cortex-M
    • GNU Toolchain
    966 views
    3 replies
    Latest over 1 year ago
     by 42Bastian Schick
  • Suggested Answer

    runtime in cortex M4 0

    754 views
    3 replies
    Latest over 1 year ago
     by GBS
  • Suggested Answer

    Cortex-M23: Dumping values on the stack 0

    677 views
    1 reply
    Latest over 1 year ago
     by 42Bastian Schick
  • Answered

    Is the bare-metal boot code for A53 also usable for A35? 0

    1095 views
    4 replies
    Latest over 1 year ago
     by asic_xuan
  • Suggested Answer

    Is there any RTOS that supports Cortex-A55? 0

    • Real Time Operating Systems (RTOS)
    • Cortex-A55
    1861 views
    3 replies
    Latest over 1 year ago
     by 42Bastian Schick
  • Answered

    DIC/IDC bit in CTR +1

    1491 views
    6 replies
    Latest over 1 year ago
     by a.surati
  • Not Answered

    How does the 4x4 Matrix Key Board on the microcontroller work 0

    676 views
    2 replies
    Latest over 1 year ago
     by 42Bastian Schick
  • Not Answered

    Cortex-A53 L2 cache invalidation 0

    • Cortex-A53
    • Cache Management
    • Cache Architecture
    1080 views
    2 replies
    Latest over 1 year ago
     by Kalex
  • Not Answered

    M7 atomic operation faults on non cacheable memory 0

    • 5 (BusFault)
    • STM32 F7
    2318 views
    8 replies
    Latest over 1 year ago
     by Clay McClure
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