A knowledgeable and self motivated Chartered Electronic Engineer with broad range of digital and analogue hardware strengths, mechanical aptitude and System Level experience. Experience of VHDL, Verilog, FPGA and circuit simulation, board design, programming in ‘C/C++’ and various other languages. A broad expertise with various embedded microprocessors and computer systems.
He has reently completed 4 years of Post Grad Research in runtime methods for approximate significance to enable adaptive image processing. Essentially identify the significant areas of an image frame and only process the most significant areas with a choice 5x5, 3x3 (or other selection) kernels, or no processing dependent on the level of significance derived from an adaptive multiple threshold level user choice.
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