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Olivier Delande

Olivier Delande

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  • Not Answered

    VMSAv8-64 Stage 2 address translation -- PA size forces use of concatenated translation tables 0

    • virtualization
    • Armv8-A
    • Memory Management Unit (MMU)
    2274 views
    0 replies
    Started over 1 year ago
     by Olivier Delande
  • Suggested Answer

    VMSAv8-64 -- worst-case effects of misprogramming of the Contiguous bit +2

    • Armv7-A
    • AArch64
    13076 views
    5 replies
    Latest over 2 years ago
     by wrw
  • Not Answered

    GICv3 ITS -- CPU accesses to GITS_TRANSLATER 0

    • pcie
    • GICv3/v4
    • Memory Management Unit (MMU)
    • System MMU
    • Hypervisor
    1984 views
    0 replies
    Started over 2 years ago
     by Olivier Delande
  • Not Answered

    Cache clean of translation tables stops execution? 0

    • Cortex-A53
    • EL3
    • Cache coherency
    • Cache
    • Armv8-A
    • Cache Architecture
    • TrustZone
    13132 views
    3 replies
    Latest over 2 years ago
     by Richard Kraus
  • Answered

    Which devices are behind the Armv8-A Base Platform FVP's SMMU? 0

    • SMMUv3
    4492 views
    6 replies
    Latest over 3 years ago
     by Olivier Delande
  • Not Answered

    GIC virtualization -- GICH_ELRSR and hardware interrupts 0

    • Generic Interrupt Controller (GIC)
    12329 views
    0 replies
    Started over 4 years ago
     by Olivier Delande
  • Answered

    GICv3 -- accessing the redistributors of other cores +1

    • Generic Interrupt Controller (GIC)
    11700 views
    2 replies
    Latest over 4 years ago
     by Olivier Delande
  • Answered

    GICv2 deactivation feature. 0

    • CoreLink GIC-400
    • Generic Interrupt Controller (GIC)
    11399 views
    3 replies
    Latest over 5 years ago
     by Olivier Delande
  • Answered

    GICv2's programming errors -- several LRs with same SGI but distinct CPUIDs 0

    • Generic Interrupt Controller (GIC)
    9580 views
    1 reply
    Latest over 5 years ago
     by Olivier Delande
  • Answered

    Write to GICv2's GICD_ITARGETSR -- wait for changes to take effects +2

    • Generic Interrupt Controller (GIC)
    4084 views
    2 replies
    Latest over 7 years ago
     by Olivier Delande
  • Answered

    Spin-lock implementation for Aarch64 -- how to enforce acquire semantics? 0

    • Armv7-A
    • AArch64
    • GNU
    14982 views
    2 replies
    Latest over 7 years ago
     by Olivier Delande