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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/"><channel><title>Nazar's Activities</title><link>https://community.arm.com/members/nazar</link><description>Nazar's recent activity</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>Jason Andrews</title><link>https://community.arm.com/members/nazar/activities/da74f1e8-e918-4c38-a05c-248f30154a77</link><pubDate>Tue, 10 Nov 2020 20:55:51 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:da74f1e8-e918-4c38-a05c-248f30154a77</guid><dc:creator>Jason Andrews</dc:creator><description>&lt;p&gt;Jason is a solutions director and distinguished engineer in the software tools group at Arm. He works with Arm partners in the areas of compilers, debuggers, performance analysis tools, and models for virtual prototyping. While at Arm, Carbon Design Systems, and Cadence he has been involved in numerous pre-silicon software development projects utilizing fast models, cycle accurate models, emulation, and FPGAs.&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Before joining&amp;nbsp;Arm, Jason &lt;/span&gt;&lt;span&gt;worked in the Electronic Design Automation (EDA) industry on various products mixing hardware simulation and embedded software execution for Simulation Technologies, Summit Design, Simpod, Axis, Verisity, Cadence, and Carbon Design Systems.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Compiler option to generate CPU log file</title><link>https://community.arm.com/developer/tools-software/tools/f/arm-compilers-forum/47996/compiler-option-to-generate-cpu-log-file</link><pubDate>Fri, 06 Nov 2020 23:04:29 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:2cb98d3b-424a-4412-a4b9-7a675b2b0271</guid><dc:creator>Nazar</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;We are using Cortex-M0+ embedded in our hardware design and would like to simulate the firmware along with the micro and the rest of the hardware using Synopsys&amp;nbsp;Verdi HW/SW Debugger which works together with Eclipse. The debugger requires an .fsdb file which can be generated from the .elf file and cpu.log file. Both, I assume can be generated during compilation. Currently only the .elf file is being generated when using this command:&lt;/p&gt;
&lt;p&gt;&lt;code&gt;/tools/compilers/arm-gcc-6.3/armv7-rpi2-linux-gnueabihf/bin/armv7-rpi2-linux-gnueabihf-gcc&lt;/code&gt;&lt;/p&gt;
&lt;p&gt;Is there a specific compile option to enable &amp;quot;cpu.log&amp;quot; file generation? I do not know how ARM referrers to this file, but the content of it should be something like:&lt;br /&gt;&lt;br /&gt; &lt;code&gt;R CPSR 000001d3&lt;/code&gt;&lt;br /&gt;&lt;code&gt; 10245 ns IE 00000000 [e59ff018] &lt;/code&gt;&lt;br /&gt;&lt;code&gt; MR4 00000020 0000003c&lt;/code&gt;&lt;br /&gt;&lt;code&gt; 10975 ns IE 0000003c [ea000011] &lt;/code&gt;&lt;br /&gt;&lt;code&gt; 11445 ns IE 00000088 [e3a00000] &lt;/code&gt;&lt;br /&gt;&lt;code&gt; R R0 00000000&lt;/code&gt;&lt;br /&gt;&lt;code&gt; 11445 ns IE 0000008c [e3a01000] &lt;/code&gt;&lt;br /&gt;&lt;code&gt; R R1 00000000&lt;/code&gt;&lt;br /&gt;&lt;code&gt; 11445 ns IE 00000090 [e3a02000] &lt;/code&gt;&lt;br /&gt;&lt;code&gt; R R2 00000000&amp;nbsp;&lt;/code&gt;&lt;/p&gt;
&lt;p&gt;Thank you for your help.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Ask A Question I</title><link>https://community.arm.com/achievements/460ac7df-7ccc-4c42-a204-9e05eef3be09</link><pubDate>Fri, 06 Nov 2020 09:29:03 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:6851f6f4-a3ff-46ff-96f2-6fc10ed882dc</guid><dc:creator /><description>Ask a question in a forum.</description></item></channel></rss>