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Matt Sealey

Matt Sealey

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  • Answered

    Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache? 0

    • Cortex-A53
    • Cache
    • Cortex-A
    20415 views
    4 replies
    Latest over 2 years ago
     by zilly
  • Answered

    range of BL instruction in arm state 0

    • Armv7-A
    • Armv7-R
    35761 views
    10 replies
    Latest over 3 years ago
     by chevestong
  • Answered

    How to specify virtual Address for pl011 uart in linux kernel 0

    • APB Peripherals
    • Arm11
    • PrimeCell UART (PL011)
    • Interrupt
    18820 views
    10 replies
    Latest over 3 years ago
     by Brayden
  • Answered

    How to set secondary core's registers from primary arm? 0

    • Cortex-A15
    • Cortex-A
    38456 views
    12 replies
    Latest over 3 years ago
     by 42Bastian Schick
  • Answered

    Flushing all L1 & L2 caches under Linux (kernel space) - optimizing dma-mapping API 0

    • Cortex-A9
    • DMA Devices
    • Linux
    20844 views
    2 replies
    Latest over 3 years ago
     by eli.z
  • Not Answered

    Loads and Stores for unaligned memory addresses 0

    • iOS
    18742 views
    2 replies
    Latest over 4 years ago
     by aketh
  • Answered

    Cortex-A7 Generic Timer Clock and Operation +1

    • Cortex-A
    • Cortex-A7
    9330 views
    4 replies
    Latest over 4 years ago
     by linda zhang
  • Answered

    armlink scatter file 0

    • Arm Compiler 6
    4648 views
    5 replies
    Latest over 5 years ago
     by Matt Sealey
  • Answered

    Non-Cacheable memory and DMA on armv7a 0

    • Armv7-A
    • Cortex-A9
    • Cortex-A
    • Cortex-A7
    10898 views
    11 replies
    Latest over 5 years ago
     by Vincent Siles
  • Answered

    Cortex M4 (SIMD) - Fastest way to un-pack 1 (one) uint32 to 4 (four) uint8 +1

    • Digital Signal Processor (DSP)
    • Cortex-M
    • Cortex-M4
    8943 views
    5 replies
    Latest over 5 years ago
     by Andrea Bettati
  • Answered

    Correct usage of the NSTable bit in aarch64/armv7a LPAE 0

    • Armv7-A
    • AArch64
    • Memory Management Unit (MMU)
    5328 views
    2 replies
    Latest over 5 years ago
     by Vincent Siles
  • Answered

    Is it possible the direct device's interrupt assignment to the guest OS instead of being routed by the hypervisor to the guest OS? 0

    • Armv8-A
    • Generic Interrupt Controller
    4847 views
    2 replies
    Latest over 5 years ago
     by Jorge
  • Answered

    ARMv8-64 Cache management in a PSCI functions 0

    • Power State Coordination Interface (PSCI)
    • Cache
    7426 views
    4 replies
    Latest over 5 years ago
     by Jorge
  • Answered

    how pc is updated during execution of SWI and any simple instruction like mov R1,R15? +1

    • R15 (PC Program Counter)
    • Armv4T
    • Arm7
    • R14 (LR Link Register)
    • Arm Assembly Language (ASM)
    9775 views
    8 replies
    Latest over 5 years ago
     by Matt Sealey
  • Not Answered

    AMP system on Cortex-A9. How to do it? 0

    • Arm Development Studio
    • Cortex-A9
    • Cortex-A
    • Arm Compiler 5
    8448 views
    1 reply
    Latest over 5 years ago
     by Matt Sealey
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