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Martin Weidmann
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Answered
aarch64 MMU: skipping first/second level tables
0
Armv8-A
6589
views
4
replies
Latest
over 3 years ago
by
Vincent Siles
Answered
generic timer difference armv8a and cortex-a53
0
5039
views
3
replies
Latest
over 3 years ago
by
heg104434
Answered
Cortex a15 disable non-blocking cache
+1
2555
views
2
replies
Latest
over 3 years ago
by
pa007
Answered
4k boundary in AXI
+1
AMBA
AXI
Interface
6853
views
2
replies
Latest
over 3 years ago
by
Martin Weidmann
Answered
command-line arguments not working in DS-5 Ultimate evaluation edition
+2
Arm Development Studio
DS-5 Ultimate Edition
6523
views
5
replies
Latest
over 3 years ago
by
ldivya47
Answered
ARMv8 Exception level on Startup
+1
EL1
Cortex-A57
ARMv8 Exception Model
EL0
Cortex-A
7401
views
5
replies
Latest
over 3 years ago
by
42Bastian Schick
Answered
Development with ARMv8a debug (and watchpoint) registers.
+1
2749
views
1
reply
Latest
over 3 years ago
by
Martin Weidmann
Answered
Processor Modes in cortex-A57
+1
Cortex-A53
Cortex-A57
Cortex-A9
AArch64
5258
views
4
replies
Latest
over 3 years ago
by
daith
Answered
The mutex implementation for TCM when using both cores-ARM9 that shares TCM
+1
2607
views
2
replies
Latest
over 3 years ago
by
dortain
Answered
Pending interrupt status
+1
Processor Architecture
Interrupt
5079
views
2
replies
Latest
over 3 years ago
by
Peter Rielly
Answered
Cortex-R7 ABT-Exception on Programstart
+1
2716
views
2
replies
Latest
over 3 years ago
by
Martin K.
Answered
A53 core does not enter sleep state with WFE
+1
3415
views
2
replies
Latest
over 3 years ago
by
blinmh
Answered
PoU (Point of Unification)
0
Armv8
3549
views
2
replies
Latest
over 3 years ago
by
Hisenberg
Answered
Zeroise complete L1 and L2 caches in ARM v8?
+2
Cortex-A53
Armv8
64-bit
3302
views
2
replies
Latest
over 3 years ago
by
SteveTickle
Answered
AXI read transfer
+1
AMBA
ACE
AXI
Interface
4702
views
1
reply
Latest
over 3 years ago
by
Martin Weidmann
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