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Martin Weidmann

Martin Weidmann

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  • Not Answered

    What are the most tangible differences between an SSD controller with Cortex-R8 and Cortex-R5? 0

    377 views
    1 reply
    Latest 6 months ago
     by Martin Weidmann
  • Not Answered

    The arm developer can't download 0

    489 views
    2 replies
    Latest 6 months ago
     by fish man
  • Not Answered

    Assembly encoding that triggers an exception in both the A32 and T32 instruction set 0

    374 views
    2 replies
    Latest 7 months ago
     by Rosario
  • Answered

    What role does the Activity Monitor (AMU) play in power and performance control? 0

    • Architecture
    • Armv8-A
    • Microarchitecture
    392 views
    1 reply
    Latest 7 months ago
     by Martin Weidmann
  • Answered

    [A-profile] Is it possible to invalidate secure physical addresses from the normal world? 0

    • AArch64
    • Armv8-A
    • A-profile
    • Cache Management
    • Memory Management Unit (MMU)
    • Cortex-A
    458 views
    2 replies
    Latest 7 months ago
     by jatron
  • Suggested Answer

    A9 - modify MMU translation table resolution 0

    517 views
    2 replies
    Latest 7 months ago
     by Atum
  • Not Answered

    MMU page table linking with relative addressing 0

    • System MMU
    366 views
    2 replies
    Latest 7 months ago
     by Niklas43
  • Answered

    CCA - Device assignment to Realm VM 0

    469 views
    2 replies
    Latest 7 months ago
     by min893
  • Suggested Answer

    Turn off prefetchers for cortex a72 0

    893 views
    4 replies
    Latest 7 months ago
     by rachelgomez123
  • Answered

    Cortex-A32 aarch32, change from HYP mode to SVC mode fail 0

    342 views
    1 reply
    Latest 7 months ago
     by Martin Weidmann
  • Answered

    [Cortex-A] Permission fault due to code region mapped as read/write 0

    • AArch64
    • Armv8-A
    • Memory Management Unit (MMU)
    • Cortex-A
    962 views
    5 replies
    Latest 7 months ago
     by jatron
  • Suggested Answer

    Arm MMU configuration works on (qemu) raspberry(a53) but not on virt(armv7, a53) board 0

    • Cortex-A53
    867 views
    6 replies
    Latest 8 months ago
     by Niklas43
  • Not Answered

    [armv8][cortex-a72] why must flush data cache when I tried to map a SRAM area? 0

    • Armv8-A
    449 views
    1 reply
    Latest 8 months ago
     by Martin Weidmann
  • Suggested Answer

    SError interrupt due to LDAXRB instruction when disable cache on NXP ls1046a 0

    • Armv8-A
    605 views
    2 replies
    Latest 8 months ago
     by Tony Tu
  • Answered

    armv8 write-back cache 0

    572 views
    1 reply
    Latest 8 months ago
     by Martin Weidmann
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