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Martin Weidmann

Martin Weidmann

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  • Not Answered

    questions about vttbr_el2 0

    • Embedded Hypervisor
    11945 views
    5 replies
    Latest 9 months ago
     by valycarrolito
  • Answered

    Program Counter, Stack Pointer and Link Register Status During an Interrupt Service in ARM based Processors +1

    2328 views
    2 replies
    Latest 10 months ago
     by Aman007kc
  • Answered

    ARM Assembly how to print numbers instead of their ascii representation of that number +1

    • Armv6
    • Arm Assembly Language (ASM)
    3846 views
    2 replies
    Latest 10 months ago
     by Kanan Jarrus
  • Answered

    How to generate delay in CPU? +1

    • Cortex-A72
    • Arm Assembly Language (ASM)
    2984 views
    6 replies
    Latest 10 months ago
     by MNB
  • Answered

    When the generic timer starts to tick? 0

    15358 views
    2 replies
    Latest 10 months ago
     by rzsz
  • Answered

    [DS-5] Is it possible to set a watchpoint on a spec reg? +1

    • DS-5 Debugger
    14721 views
    1 reply
    Latest 10 months ago
     by Martin Weidmann
  • Not Answered

    Arm Really Should Standardize An SMC Interface For Hardware Random Number Generators 0

    • Arm Trusted Firmware
    • SMCCC
    • Server Base System Architecture (SBSA)
    15049 views
    2 replies
    Latest 11 months ago
     by myfreeweb
  • Answered

    Debug Unit Cortex - R 0

    2480 views
    3 replies
    Latest 11 months ago
     by Martin Weidmann
  • Answered

    ARM Cortex A5 -Issue: Undefined Instruction when write/read value of CNTFRQ register in core ARMv7 0

    14832 views
    2 replies
    Latest 11 months ago
     by Khuong Nguyen
  • Not Answered

    Need interrupt handling code for ARM cortex A9 0

    14677 views
    3 replies
    Latest 11 months ago
     by Tejadeep
  • Answered

    TLB Conflict abort 0

    10742 views
    3 replies
    Latest 11 months ago
     by Martin Weidmann
  • Answered

    FVP License 0

    • AEMv8 FVP
    12370 views
    8 replies
    Latest 11 months ago
     by Bill M
  • Answered

    Memory barrier when accessing strongly ordered memory +1

    2276 views
    3 replies
    Latest 11 months ago
     by Martin Weidmann
  • Answered

    why the inter-core SGI interrupt cannot be trigged on GICv3 hardware 0

    • Generic Interrupt Controller (GIC)
    17084 views
    9 replies
    Latest over 1 year ago
     by MSK
  • Answered

    Synchronization of caches on ARMv8 0

    • Armv8-A
    12341 views
    2 replies
    Latest over 1 year ago
     by Martin Weidmann
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