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Martin Weidmann

Martin Weidmann

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  • Answered

    What is all possible SGI miss scenario? 0

    • GICv3/v4
    • CoreLink GIC-600 Generic Interrupt Controller
    • Generic Interrupt Controller
    • CoreLink GIC-600AE
    801 views
    11 replies
    Latest 1 day ago
     by Martin Weidmann
  • Answered

    Using stage 2 translation for VMs and stage 1 translation for native applications in the same system +1

    • virtualization
    • Memory Management Unit (MMU)
    234 views
    4 replies
    Latest 7 days ago
     by Borna
  • Suggested Answer

    ARMV7 PMU event counter always return 0 0

    295 views
    6 replies
    Latest 7 days ago
     by Lico.yu
  • Suggested Answer

    M55 System Counter & System Timer register map html/xml request 0

    274 views
    1 reply
    Latest 9 days ago
     by Martin Weidmann
  • Suggested Answer

    Dual A53 cluster, MMU configuration 0

    290 views
    4 replies
    Latest 9 days ago
     by Majid Ghameshlu
  • Answered

    Generic Timer IRQ Handling 0

    • GICv3/v4
    263 views
    3 replies
    Latest 11 days ago
     by Martin Weidmann
  • Suggested Answer

    Bare metal - EL2 to EL1 - SP behaviour 0

    540 views
    6 replies
    Latest 17 days ago
     by Martin Weidmann
  • Answered

    Interrupt Handling recommendation and spurious IRQ debugging 0

    • GICv3/v4
    • ARMv8 Exception Model
    252 views
    1 reply
    Latest 29 days ago
     by Martin Weidmann
  • Answered

    GICv2 vs GICv3 differences 0

    • GICv2
    • GICv3/v4
    290 views
    1 reply
    Latest 1 month ago
     by Martin Weidmann
  • Answered

    Linux SGI's on quad Cortex-A53 0

    378 views
    3 replies
    Latest 1 month ago
     by andreas2025
  • Answered

    How peripherals are accessible between NW and SW? 0

    • SMMUv3
    • Peripheral Controllers
    • TrustZone
    202 views
    1 reply
    Latest 1 month ago
     by Martin Weidmann
  • Answered

    Migration from Cortex M4 to Cortex R5F 0

    • Software
    • Cortex-R5
    • Cortex-M4
    339 views
    3 replies
    Latest 1 month ago
     by Ryleigh Sawayn
  • Answered

    Reading Cortex-A9 CNTFRQ register using ARM Compiler 5 inline assembly 0

    • Cortex-A9
    • Arm Assembly Language (ASM)
    • Arm Compiler 5
    898 views
    7 replies
    Latest 2 months ago
     by Martin Weidmann
  • Not Answered

    What is the default FPU in ARMv8? 0

    • AArch64
    • Armv8-A
    • NEON
    • Floating Point
    • AArch32
    358 views
    2 replies
    Latest 2 months ago
     by pedrobotelho15
  • Answered

    Any global register in ARMv8? 0

    • AArch64
    • Armv8-A
    317 views
    2 replies
    Latest 2 months ago
     by zy_cloud
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