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<?xml-stylesheet type="text/xsl" href="https://community.arm.com/utility/feedstylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/"><channel><title>Morrissey_82's Activities</title><link>https://community.arm.com/members/morrissey_5f00_82</link><description>Morrissey_82's recent activity</description><dc:language>en-US</dc:language><generator>Telligent Community 10</generator><item><title>gnu GCC option to enforce 8-byte stack alignment (necessary for R52)?</title><link>https://community.arm.com/developer/tools-software/oss-platforms/f/gnu-toolchain-forum/47734/gnu-gcc-option-to-enforce-8-byte-stack-alignment-necessary-for-r52</link><pubDate>Mon, 28 Sep 2020 21:06:00 GMT</pubDate><guid isPermaLink="false">dd9e70c8-6d3c-4c71-b136-2456382a7b5c:7d89cc3c-6b30-46e5-9aee-8397e5e46bec</guid><dc:creator>BenjaminEhlers</dc:creator><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;ARM support and R52 TRM have indicated that the R52 core requires maintaining an 8-byte aligned Stack (meaning compiler shall always push/pop registers in even numbers), and I see in my current setup the GNU GCC compiler is not adhering to that requirement. Subsequently in my core simulations I see R52 erroneous behavior if the stack is not maintained as such, especially if only a single register is pushed/popped for a function.&lt;/p&gt;
&lt;p&gt;Am I missing some GNU GCC option to force 8-byte stack alignment? Also since ARM support stated this was a necessary requirement, shouldn&amp;#39;t that be automatically implemented in the &lt;strong&gt;-mtune=cortex-r52&lt;/strong&gt; options?&lt;/p&gt;
&lt;p&gt;My current setup is using ARM recommended version&amp;nbsp;gcc-arm-none-eabi-9-2020-q2-update (according to the GNU toolchain developer website)&lt;/p&gt;
&lt;p&gt;(I have also tested the version&amp;nbsp;gcc-arm-none-eabi-10-2020-q2-preview, still seeing same problems)&lt;/p&gt;
&lt;p&gt;My GCC command has the following options:&lt;/p&gt;
&lt;p style="padding-left:30px;"&gt;gcc-arm-none-eabi-10-2020-q2-preview/bin/arm-none-eabi-gcc -march=armv8-r -mfpu=neon-fp-armv8 -mtune=cortex-r52 -marm -c -g -O3 -fno-inline -fno-strict-aliasing -DGCC -falign-functions=16 -falign-jumps=8 -falign-loops=8 -fomit-frame-pointer -funroll-loops -mapcs-frame -DITERATIONS=20 -save-temps -DCR52 -Werror -Wall -Dcr52 -DCORE_0 -std=c99 -o alive_CORE_0.o -c alive.c&lt;/p&gt;
&lt;p&gt;From above example, my compile results in the following odd-number of registers pushed onto stack: (see snippet from .lst file)&lt;/p&gt;
&lt;p style="padding-left:30px;"&gt;int main (void) {&lt;br /&gt; 2a980: e92dd810 &lt;strong&gt;push {r4, fp, ip, lr, pc}&amp;nbsp;&amp;nbsp;&lt;/strong&gt; &amp;lt;&amp;lt;&amp;lt;=== ODD NUMBER OF REGISTER IN PUSH INSTRUCTION:&lt;/p&gt;
&lt;p&gt;NOTE: the problem also occurs if I use -mthumb mode.&lt;/p&gt;
&lt;p&gt;Other notes: I added the -fno-inline as according to an internal verification decision that we want to avoid the code in-lining optimization. Additionally I added the -mapcs-frame in an attempt to fix this issue, and this option seems to make the problem a lot better, but doesn&amp;#39;t completely fix the problem.&lt;/p&gt;
&lt;p&gt;Or is this a&amp;nbsp;GNU GCC bug for the -mtune=cortex-r52 set of tuning options?&lt;/p&gt;
&lt;p&gt;Thanks in advance for any help.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>