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geekfolk

geekfolk

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  • Answered

    why the inter-core SGI interrupt cannot be trigged on GICv3 hardware 0

    • Generic Interrupt Controller (GIC)
    31085 views
    10 replies
    Latest over 1 year ago
     by ivan_m@rocketmail.com
  • Answered

    CortexA8 L2 data loss 0

    • Cache
    • Cortex-A
    • Cortex-A8
    22607 views
    23 replies
    Latest over 7 years ago
     by Andreas Hauser
  • Answered

    What will happen if one core sends SGI interrupt to another core quickly and continuously？ 0

    • Generic Interrupt Controller (GIC)
    4945 views
    2 replies
    Latest over 7 years ago
     by geekfolk
  • Answered

    a appropriate CortexA15 development board +1

    • Cortex-A15
    • Cortex-A
    4999 views
    4 replies
    Latest over 7 years ago
     by geekfolk
  • Answered

    ARMv8 Secure EL1 problem 0

    • EL1
    • Armv7-A
    • Armv8-A
    • AArch32
    12989 views
    8 replies
    Latest over 8 years ago
     by Martin Weidmann
  • Answered

    Aarch64 / Aarch32切换问题 0

    • Processor
    • chinese
    • AArch64
    • 中文
    • AArch32
    • 处理器
    13274 views
    13 replies
    Latest over 8 years ago
     by geekfolk
  • Answered

    the UART char print in ARM v8-A Foundation Platform 0

    • Armv8-A
    • Linux
    4856 views
    2 replies
    Latest over 8 years ago
     by Yasuhiko Koumoto
  • Answered

    ARM TrustZone's Secure/Normal world vs x86's Ring0/3 or OS's kernel/user mode? +1

    • TrustZone
    • Linux
    9028 views
    2 replies
    Latest over 8 years ago
     by daith
  • Answered

    What will I get if I try to access SCR in cp15 when my core is in non secure mode. +1

    • TrustZone
    5314 views
    4 replies
    Latest over 8 years ago
     by Jay Zhao