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Colin Campbell
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Not Answered
axi problem
0
652
views
1
reply
Latest
3 months ago
by
Colin Campbell
Not Answered
Help with AXI4 payload with data bus width of 32 bits
0
AXI4
4472
views
1
reply
Latest
3 months ago
by
Colin Campbell
Not Answered
Question related to Phases in APB
0
4351
views
1
reply
Latest
4 months ago
by
Colin Campbell
Not Answered
HTRANS for HBURST == SINGLE
0
6701
views
2
replies
Latest
5 months ago
by
Colin Campbell
Not Answered
can we delay read and write transactions(axi4) by providing delay in register slice?
0
AXI4
79045
views
67
replies
Latest
6 months ago
by
casseverhart13
Answered
WSTRB calculation
0
7223
views
2
replies
Latest
6 months ago
by
Ravi V.
Not Answered
AMBA AHB HRDATA signal behavior
0
7474
views
1
reply
Latest
6 months ago
by
Colin Campbell
Answered
Handshaking for the write data channel
0
7400
views
3
replies
Latest
7 months ago
by
Colin Campbell
Suggested Answer
BUSY transfer and WAIT state both are using the same time ,How to perform the AHB?
+1
AHB
11655
views
2
replies
Latest
7 months ago
by
Mukul_Prajapati
Not Answered
AXI3 locked access
+1
AMBA
AXI
9501
views
3
replies
Latest
7 months ago
by
Colin Campbell
Answered
Difference btw AXI3 and AXI4
0
AMBA
AXI3
AXI4
Interface
20219
views
6
replies
Latest
7 months ago
by
Colin Campbell
Answered
WID not present in AXI4
0
6596
views
1
reply
Latest
7 months ago
by
Colin Campbell
Answered
FIXED WRITE transfer of AWLEN=8'd4 in AXI4
0
6459
views
1
reply
Latest
7 months ago
by
Colin Campbell
Answered
Handling invalid AXI address requests
0
AXI4-Lite
Cortex-M System Design Kit
Cortex-M
7179
views
1
reply
Latest
7 months ago
by
Colin Campbell
Answered
AXI INC type transfer
0
6798
views
2
replies
Latest
7 months ago
by
Ravi V.
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