Giacomo joined Arm in 2010 and since then he has contributed to extensions to the Arm architecture, in particular the Scalable Vector Extension (SVE), and has been involved in various performance modelling activities, mostly based on the gem5 simulation framework.
He currently leads a research team focused on architectures for general-purpose and specialized applications. His research interests include performance modelling, parallel and vector processing, and domain-specific architectures and compilers.
In his PhD at the University of Pisa he explored performance and efficiency optimizations for cache memories with non-uniform access times.
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