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a.surati

a.surati

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  • Answered

    How writing ICC_EOIR1_EL1 works for Group 1 Interrupts when running on EL3 in GICv3? 0

    • GICv3/v4
    • ARMv8 Exception Model
    • Armv8-A
    • TrustZone
    645 views
    2 replies
    Latest over 1 year ago
     by MHesham
  • Answered

    Dynamic post quality detection +1

    3712 views
    1 reply
    Latest over 1 year ago
     by Oliver Beirne
  • Answered

    TTBR0_EL1 translation fault level 3 on 4KiB blocks where 2MiB blocks work. 0

    • Armv8-A
    • System MMU
    910 views
    3 replies
    Latest over 1 year ago
     by a.surati
  • Answered

    What is int_width about in arm_nn_activations_direct_q7 about +1

    • Machine Learning (ML)
    • Arm NN
    1956 views
    9 replies
    Latest over 1 year ago
     by a.surati
  • Answered

    TTBR0_EL1, translation fault level 0 after switching identity mapping off 0

    • Armv8-A
    1573 views
    6 replies
    Latest over 1 year ago
     by MrMino
  • Answered

    For a same virtual address, does the secure EL1/0 and non-secure EL1/0 see the same physical address? 0

    • secure systems
    • Armv8-A
    • Memory Management Unit (MMU)
    710 views
    2 replies
    Latest over 1 year ago
     by asic_xuan
  • Answered

    Which GIC does Armv-A Base RevC AEM FVP implement? 0

    • GICv3/v4
    • Fixed Virtual Platforms (FVPs)
    727 views
    1 reply
    Latest over 1 year ago
     by a.surati
  • Not Answered

    Static variables failing to initialize using libgcc/libstdc++ 0

    983 views
    4 replies
    Latest over 1 year ago
     by anotherPoet
  • Not Answered

    #pragma push , is not supported by ARM Compiler 6, what should I do ? 0

    1691 views
    5 replies
    Latest over 1 year ago
     by a.surati
  • Answered

    No LDREX/STREX-based implementations of __cxa_guard_acquire/release/abort in ARM code? 0

    • C++
    • abi
    1292 views
    4 replies
    Latest over 1 year ago
     by Alain Mosnier
  • Answered

    DIC/IDC bit in CTR +1

    1491 views
    6 replies
    Latest over 1 year ago
     by a.surati
  • Answered

    ICPR usage in Arm Cortex m4 +1

    • Cortex-M4
    867 views
    2 replies
    Latest over 1 year ago
     by Yorker Hazan
  • Not Answered

    Linking with arm-none-eabi-gcc instead of arm-none-eabi-ld 0

    • GCC
    • GNU Arm
    3869 views
    2 replies
    Latest over 1 year ago
     by WestfW
  • Answered

    Cortex-A15 Cache Maintenance DCIMVAC vs DCCIMVAC 0

    • Cortex-A15
    • Cache Management
    1228 views
    3 replies
    Latest over 1 year ago
     by Dylan1234
  • Answered

    armclang and memcpy: Weird behavior 0

    • Arm Compiler 6
    • Cortex-M7
    • Armv7-M
    3275 views
    11 replies
    Latest over 1 year ago
     by a.surati
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