• ARM NEON optimization

    Welcome to the ARM NEON optimization guide!

    1. Introduction

    After reading the article ARM NEON programming quick reference, I believe you have a basic understanding of ARM NEON programming. But when applying ARM NEON to a real-world applications, there…

  • ARMv8 EL1 MMU

    Hi,

        I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1.

    I am not able to set sctlr_el1.M bit when ever i try to set this bit the instruction won't complete. I think it…

  • ARMv8 mmu problem

    Hi ARM experts,

    I have a problem in using armv8 mmu in bare-metal system:

    When using the 4KB translation granule, level 1 table which use D_Block convert VA to 1GB region PA.

    In Armv8 ARM page D4-1744, table lookup starts at level 0.

    Is the Level 0 table…

  • Cortex-M7 Load/store timing execution ?

    I'm not a native English speaker. So, sorry for the broken English. I'm intend to develop a system where the microcontroller will interface with a 8 bit parallel port IC. The bytes will be loaded into the microcontroller at the specific timing. As documented…

  • Divide and Conquer

    Division on ARM Cores

    “At the end of the day, we must go forward with hope and not backward by fear and division.” – Jesse Jackson.

    It often surprises me how many people believe that “ARM doesn’t do division” or “ARM cores don’t have…

  • Enable MMU and d-cache on ARMv8 for u-boot

    Hi,
    This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory. The dump is shown below
    "Synchronous Abort" handler…

  • GIC500 :: How to forward interrupts to multiple cores using GICD_IROUTER

    Is there a way to forward the interrupts from Descriptor to multiple Cores using GICD_IROUTER ?

    Seems the Affinity Routing field in my case is hard-tied to 1.  


    P.S. The SoC I'm working on, do have 8 ARM cores

  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

    hi :

    I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

    however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

    and I saw some points that L2 flushing was not needed.

    for ARMv8,  how can…

  • Programmable Interrupt Controllers: A New Architecture

    A programmable interrupt controller is an IP block that collates many sources of interrupt one one or more CPU lines, as well as submitting a level of priority to the interrupt outputs. It’s fair to say that almost every SoC needs an interrupt controller…