Arm CoreLink PCK-600 enables efficient and rapid integration of SoC power management infrastructure

Power Control Challenges

A modern SoC requires efficient power control infrastructure to provide maximum performance with minimum required power. Arm is the leader in low power innovation and architecture, from Arm big.LITTLE to the latest Arm DynamIQ clusters. As the power domain and operation modes become more granular, on-chip power management presents more complexity and takes more time to implement.

Taking a mobile SoC as an example, in addition to the processing elements, communications and common system functionalities there is usually an "always-on" domain which contains the power controller functions that need to remain active even in SoC sleep states. There are coordination challenges related to this power control function, as the complexity of power and thermal management increases. These challenges arise because there are many elements to manage, including clock and voltage supplies, power domains, sensor inputs, events and so on.

Another significant challenge is the integration of power management infrastructure across the SoC. This infrastructure is pervasive, and requires ensuring that all components participate in clock and power domain management. Arm describes an approach to power infrastructure integration in the Arm Power Control System Architecture (PCSA) specification, where standard infrastructure components are used. These components constitute the new Arm CoreLink PCK-600.

Arm CoreLink PCK-600

CoreLink PCK-600 is a collection of standardized and pre-verified Arm IP which is implemented to the Arm Low Power System Architecture specification. It is developed based on the P and Q-Channel Low Power Interface (LPI) standard. LPI has been widely adopted by Arm partners, who also implement it in their own IP, which needs to work with Arm IP. CoreLink PCK-600 is delivered with the following components:

  • Power Policy Unit (PPU)
  • Clock Controller (CC)
  • Q-Channel Distributor (LPD-Q)
  • P-Channel Distributor (LPD-P)
  • Q-Channel Combiner (LPC)
  • P-to-Q Convertor (P2Q)

Top-level example integration of all PCK-600 components to the SoC

Top-level example SoC integration of PCK-600 components

Power Policy Unit (PPU)

The Power Policy Unit (PPU) is a standard component for abstracting software controlled power domain policy down to low level hardware control signalling. In a typical arrangement, one PPU is used to control each power gated domain. The System Control Processor (SCP) firmware can program the power policy of a PPU. This policy can be either a static power mode, or a range of modes that the PPU can transition between dynamically. This dynamic behaviour is based on activity indicators from component LPIs without the need for further SCP programming. This enables hardware autonomous modes, such as dynamic retention, which can be entered and exited transparently to software. This provides responsive power control enabling components to be in the lowest power state possible, while maintaining functionality, with only policy level control from the SCP. A typical SCP to PPU integration would look something like the following, where the SCP is orchestrating power management through:

  • Embedded microcontroller for power management
  • Arm SCMI for commands from OS and other agents
  • SCP is system aware – reconciles SW and platform constraints to select optimal policy
  • Hardware assist from PPU for autonomous power transitions

Power domain management with the Power Policy Units

Example power domain management with the Power Policy Units

Clock Controller (CC)

The clock controller is used to provide high-level clock gating for components in a clock domain that have either Q-Channel LPI clock gating support, or AXI LPI clock gating support. The clock controller combines LPIs from multiple components to manage a single clock domain. It uses the LPIs to ensure all components are in a quiescent state before the clock is gated. It also ensures the clock is running again before any component leaves the quiescent state.

The clock controller allows LPIs to be controlled asynchronously so that the synchronous clock enable from the clock controller can be applied to a clock gate at the root of the clock tree. This high-level clock gating can result in near zero dynamic power in idle scenarios and does not exclude any clock gating from being implemented inside components at a finer granularity.

Power Control Distribution and Conversion

The power distribution network across the SoC is implemented through a chain of connectors and convertors that help combine or distribute P-channel and Q-Channel LPIs. For instance, LPD-Q is used to expand a single controller Q-channel into multiple component Q-Channels. The same applies to LPD-P as a P-channel distributor component. Where there are components which have dependencies on the state of multiple power domains, the LPC is used to combine the Q-Channels from the relevant domains to mediate the correct power sequencing. The P-to-Q convertor is used to facilitate operations between different pieces of IP which have different low power interface standards.

Summary

As a summary, CoreLink PCK-600 provides the following benefits:

  • Highly configurable pre-verified power and clock infrastructure IP
  • Standard Arm Low Power Interface implementation
  • Interoperable with all Arm IP
  • Standard software interface
  • Arm Socrates tooling support for ease of IP integration

To request for more information on CoreLink PCK-600, please visit:

PCK-600 product page

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