Design time verification practices such as Register Transfer Language (RTL) simulation and formal coverage verification may still not be able to uncover all bugs in a design. The problem is aggravated with the increase in SoC complexity which integrates a condensed set of IP onto a single SoC, as the chances of escaped design bugs increase consequentially. Hence, post-silicon functional debug is key to quickly locating any undetected design flaws.
Arm CoreSight Embedded Logic Analyzer IP is designed to provide extra assistance in silicon post-deployment debug in the field by monitoring low level hardware signals which emulate design time simulation debug. For the background on the introduction to the first generation of the product family (ELA-500), please refer to ELA-500 debug with DS-5 and CoreSight ELA-500 webpage
Arm CoreSight ELA-600 is the next generation Embedded Logic Analyzer that extends the functionality of ELA-500 by including an external trace data output interface, this interface implements the AMBA Trace Bus (ATB) protocol. One major advantage offered through the addition of this interface is the ability to trace large amounts of signal data, limited only by trace memory storage capacity either on-chip or off-chip. The ELA-600 is designed to be backward compatible to ELA-500 by supporting the same embedded SRAM configuration. ELA-600 adds support for a 256-bit comparator for the input signals whilst each trigger state comparator can also be segmented into multiple 32-bit comparators to allow for greater comparison granularity for logic analysis and signal tracing. Other advanced features added to ELA-600 are summarized in the following table.
CoreSight ELA-600 allows you to identify hard-to-diagnose bugs quickly which accelerates silicon bring-up.
ELA-600 can be instantiated across the SoC mainly with the purpose of aggregating signal information for monitoring and debug purposes. Each ELA-600 can be configured to output to an individual ATB interface that is then funnelled into the same trace sink component. This data can then be stored either on-chip or directed to an external debug client. The main benefit of this implementation choice is to be able to trace the signals that are attached to individual ELA-600 instances when needed.
One of the reasons for implementing ELA-600 in a hierarchical manner is to help segregate the SoC into different target regions. This makes it easier to debug different areas of an SoC. The following diagram implements the ELA-600 in groups that output a single trace or action from the traffic initiators (masters), receivers (slaves) and system control processors. The other benefit of this integration method is reducing the amount of wire distribution across the SoC where output from the intermediate ELA-600 may only be a single wire output feeding into the next ELA-600 as a trigger input or through the cross-trigger interface (CTI).
For IP that is implemented in lock-step topology, the CoreSight ELA can be used to monitor and compare functional differences between the two replicated IP through bus transaction trace or Performance Monitoring Unit (PMU) trace. Additional insight into the lock-step IP can be obtained through CoreSight code being traced such as speculative cycles, request to response delays and snoop delays etc.
The conventional method of debug for a hang or lock-up scenario is performed through scan chain scan dump analysis. This method is slow and tedious as the data observed is very constrained in terms of observable timing window. CoreSight ELA shortens the debug cycle by enabling chip designers to target the area that is prone to failure and hence limiting the amount of traceable data. For instance, using ELA to monitor snoop traffic to determine whether a snoop response was not received and then trigger the necessary action.
When data corruption occurs in the memory due to incorrect data being transmitted, the data can be traced back to its source through monitoring transactions from the intended traffic initiator on-chip. This is especially beneficial for the case where the initiator IP is less mature and prone to design errors.
Complex integrated SoCs often require highly efficient power management infrastructure to improve system performance and efficiency. Power and clock control network can be tracked and monitored for unexpected sequences causing drastic voltage-drops across certain areas of the SoC. This can be set as a trigger point to observe voltage variation and functional deficiency.
As with new IP designs which may be susceptible to design errors when deployed in different applications, analogue interfaces such as PCIE PHY, DDR PHY are also prone to design flaws when implemented on a new silicon fabrication process. CoreSight ELA can be used to monitor and distinguish between logical versus analogue failures, thus identifying SoC failures due to an ATE test coverage hole.
The ELA-600 can be used to characterize performance through high-precision latency measurements and event counts. For instance, performance can be monitored by using ELA-600 trigger state condition comparisons and counters to measure and trace the cycle count between wait state latency ,from VALID to READY assertion for a read or write transaction.
In an embedded environment, where asynchronous sensor interrupts frequently wake the CPU, an ELA-600 could be used to offload simple if/then filtering that might otherwise have to be performed by a CPU in an interrupt service routine – thus saving power by not having to awaken the CPU core.
A typical smart thermostat might operate as follows:
Such a sequence could be handled by the ELA-600 instead of the CPU. This could be achieved by configuring the ELA-600 with 2 trigger states and an ELAOUTPUT action, provided the ELA-600 has inputs from the motion sensor and temperature sensor.
The following pseudo code illustrates some ELA-600 capabilities.
ELA-600 extends the usage model of the previous generation of CoreSight ELA IP by improving trace depth thus enabling a larger debug window. This, together with other enhancements, significantly improves signal tracing efficiency and accelerates results computation for downstream interpretation.
For more product information on Arm CoreSight ELA-600, please visit our webpage.