Energy is a precious resource, which should not be wasted. Energy drives economies and sustains societies.
Predictions show that the energy of electronics may soon consume 20% to 33% of the global energy supply, as it is highlighted in this blog post about "Design and Manufacturing in 2030" from Greg Yeric, fellow at Arm.
Energy efficiency is such an important global issue that it is one of the UN's 17 Global Goals for Sustainable Development; the world's to do list to safeguard and support prosperity for people and planet. Goal 7 includes, among other targets, a target to double the improvement in energy efficiency by 2030.
Arm has taken a very active role in the delivery of the Global Goals since their inception in 2015, founding the 2030Vision initiative to convene the technology sector in support of the Goals. Energy-efficiency considerations need to be built into technology and product design from the outset - at the design stage. One of Arm's contribution is to provide energy-efficient IPs (Intellectual properties). These IPs allow integrated circuit to draw less electricity, to work on energy harvesting capabilities or to use batteries for a longer period of time, therefore reducing waste. To be able to deliver even more energy-efficient products, some parts of an integrated circuit development and associated tools require a specific focus on energy.
In this blog post, we scratch the surface of what needs to change from a physical design perspective to deliver more energy efficiency for digital designs, in terms of mindset but also in terms of technology.
One of the challenges is that for years power has been implicitly used as a proxy for energy. With fixed or very high performance to hit, we often hear about how to develop power efficient designs, how to optimize for power or even how to perform power recovery. But in the end, it is most of the time about producing energy-efficient IPs, not just power efficient IPs.
Let us go back to basics to understand the nuance:
The energy metric can inform us, for example, about the time it takes for a task to complete in a specific power state or how long a device can run with a battery size. Getting better overall energy, it is about minimizing power, or completing tasks faster (higher performance), or the third option could also be a compromise between reducing power and reaching high performance.
Energy is actually a crucial metric for several market segments such as IoT, Mobile, Machine Learning inference at the edge or even Infrastructure to name a few. One complex aspect resides in the variety of software contents that could be run on an IP. These contents all have different power profiles over time and activate different parts of the design lightly or heavily. The final energy consumption of a device in real life is very dependent, among other factors, on use-time and type of workload.
Obviously, there are more chances to influence energy efficiency at the early stages of an IP development, that is, from architecture and micro-architecture. But later in the digital integrated circuit development flow there is a great potential to achieve better energy efficiency with a different focus applied. Electronic Design Automation tools have seen a progressive change in priorities over the years concerning PPA (Power, Performance, and Area) but there is still room for ground-breaking innovation to happen.
Some questions can help to understand what a different focus on power & energy could enable to achieve:
Designing an IP or a chip is usually an iterative process. Keeping in mind that achieving high energy efficiency is an goal could lead to different solutions, compared to focusing on reducing power when possible. An example of this approach put in practice has been demonstrated by Seng Oon Toh and James Myers from Arm. They wrote a technical paper on "Minimum Energy Design for Subthreshold Wireless Sensor Nodes" published in 2015 at the SNUG conference (link). One of their conclusions shows that an energy-centric implementation could lead to an impressive reduction in energy.
Basically, two axes can be followed to constantly address energy in physical implementation:
The following picture shows the main aspects which could be part of an energy driven flow following the two axes quoted previously.
It starts with selecting the relevant stimuli (switching activity inputs) or creating synthetic ones. The stimuli allow power & energy analysis but also act as very important inputs for synthesis and place&route tools, so optimization can be performed accordingly. The switching activity used to optimize power is arguably the most important key for success. Several types of IPs run very different pieces of software, therefore different parts of the design are more or less utilized. Nowadays between industry benchmarks, real use cases and future contents, it is very complex to optimize an IP for the relevant set of switching activity inputs. The optimization achieved might be only as good as the switching activity inputs selection.
Two different high-level types of power & energy analysis can be done, depending if it is early or late in the design flow. Estimating power & energy directly on hardware description (RTL, output from High-Level Synthesis or other hardware models) is faster but with the caveat that it does not obtain fully accurate absolute values. It can though give good indications on trends, that is, is power & energy going up or down depending on changes made in the hardware description code. Measuring power on netlists is of course giving more confidence in the data, but the waiting time to get data is longer as the design needs to complete fully or partially the physical implementation flow.
At any point in time a feedback loop should exist to update the hardware description or parts of the physical implementation flow based on intelligence applied on the power & energy data obtained (power inspection). Static checks and also more sophisticated dynamic checks (requiring switching activity inputs) can be seen as a complement to the brain power of engineers to get additional power & energy efficiency.
Power optimizations should be at the heart of synthesis and place&route engines, always enabling the user to choose between power and performance. The decisions made when entering the physical design world tend to be static and are rarely revisited later in the flow. That is why the inputs to physical implementation are important things to get right, for example:
The most energy-efficient implementation might not come at the lower voltage or at the highest frequency. There is a right compromise to be had between power and performance to get an energy optimized answer. It is all about the "area" of the power profile over time. This requires a smart sweep over different PPA targets and libraries to be performed.
Finally, a potential energy driven physical implementation flow could look like this:
More designs intended for specific markets treat energy as a first-class metric. The choice to optimize for minimal power or best energy efficiency should be available to users. This is a challenge knowing how current EDA tools operate, with performance coming first most of the time. But it is also an incredible opportunity to innovate and to contribute to the wider picture for overall better energy efficiency in the world.
We must remember that even a few millijoules saved on a design matter, as we talk about billions and billions of devices soon to be powered and enabled everywhere.
(some pictures in this blog post are re-used from other Arm presentations and colleagues, credits among others to James Myers).