Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Forums
Forums
SoC Design and Simulation forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 751 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • TOSA forum

  • Answered

    What is expected from response if in WRAP txn in AHB is un-aligned. +1

    • AHB-Lite
    • AHB
    14375 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AMBA +1

    • APB
    • AMBA
    • Bus Architecture
    14152 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Does AHB-Lite Protocol require the master processor to be pipelined? +1

    • AHB-Lite
    • Processor Architecture
    16296 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    APB process when pstrb = "0000" or "0101" during write transaction 0

    16201 views
    2 replies
    Latest over 7 years ago
    by Hyunkyu
  • Not Answered

    Dealing with Inout Ports - design and testbench writing 0

    • Verilog
    12247 views
    0 replies
    Started over 7 years ago
    by Kedhar Guhan
  • Answered

    How do I add AHB interface to a processor with Load Store Architecture? 0

    • Processor Architecture
    • AMBA 2 AHB Interface
    • AHB
    15527 views
    2 replies
    Latest over 7 years ago
    by Kedhar Guhan
  • Not Answered

    Axi4 Write Transaction 0

    • AMBA
    • AXI4
    14452 views
    1 reply
    Latest over 7 years ago
    by vstehle Arm Employee Badge
  • Not Answered

    State Machine for AHB-Lite Protocol 0

    • AHB-Lite
    • AHB
    17203 views
    3 replies
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? +1

    • AXI
    17316 views
    2 replies
    Latest over 7 years ago
    by Zax
  • Not Answered

    Assertion for Multiple Transfer on APB Bus 0

    • APB
    • AMBA
    • Bus Architecture
    15405 views
    2 replies
    Latest over 7 years ago
    by Rakesh Venkatesan
  • Answered

    What purpose do wrapping BURST transfers serve? +2

    • AHB-Lite
    • AHB
    24646 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Can a simple processor with load-store architecture support BURST? 0

    • AHB-Lite
    • Processor Architecture
    • AHB
    14111 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Why does an AHB slave require HBURST signal? 0

    • AHB
    • Memory
    17503 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    What purpose does BURST feature in AHB serve? 0

    • Protocols
    • Architecture
    • AHB-Lite
    • Processors
    • AHB
    23911 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Is there any scenario where HWDATA and HRDATA are used simultaneously? 0

    • AMBA 3 AHB Interface
    14107 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Bypassing all clock gates in Cortex-R52 (ARMv8) 0

    • Cortex-R52
    • FPGA
    12683 views
    0 replies
    Started over 7 years ago
    by Zack Yang
  • Not Answered

    [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! 0

    • GICv3/v4
    • Generic Interrupt Controller
    14160 views
    1 reply
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    One question about the power pin connection on Arm Artisan 14nm 14LPP High-Speed Single-Port SRAM 0

    13007 views
    0 replies
    Started over 7 years ago
    by binbin
  • Suggested Answer

    When should APB slave Sample address/Data for read/write transaction from APB master? 0

    27920 views
    5 replies
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    AXI 4 UPsizer Downsizer module's protocol checker Error with WSTRB? 0

    14199 views
    2 replies
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
<>