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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3657 Questions
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  • Not Answered

    Where can I find the sc300 Technical reference manual? 0

    5734 views
    2 replies
    Latest over 6 years ago
    by YimoYimo
  • Answered

    Best way to safely check if virtual address exists 0

    23124 views
    4 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Is it necessary to flush data cache of a modified page table entry? 0

    • Memory Management Unit (MMU)
    22082 views
    1 reply
    Latest over 6 years ago
    by astonelin@gmail.com
  • Answered

    Old startup .s files from DS-1, etc. 0

    20042 views
    2 replies
    Latest over 6 years ago
    by smblackledge
  • Answered

    cortex m4 IP 0

    4882 views
    5 replies
    Latest over 6 years ago
    by Andy Neil
  • Answered

    can we delay read and write transactions(axi4) by providing delay in register slice? 0

    • AXI4
    133525 views
    67 replies
    Latest over 6 years ago
    by casseverhart13
  • Not Answered

    MPU config and memory attributes 0

    • Cortex-M7
    • STM32
    • STM32 F7
    10183 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Transition from EL3 to EL1 on A53 0

    20908 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex-A35 cache partitioning 0

    • Cache
    • Cache Management
    • Cache Architecture
    20257 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Bare Metal I/O documentation help 0

    19510 views
    3 replies
    Latest over 6 years ago
    by Andy Neil
  • Answered

    Transmitting and reconstructing DSP data over internet. 0

    6392 views
    6 replies
    Latest over 6 years ago
    by Phalelashvili
  • Not Answered

    Cycle accurate Cortex-M3 simulator using obsfucated RTL 0

    • Cycle Models
    • Cortex-M3
    • Hardware Modelling/Simulation
    5905 views
    2 replies
    Latest over 6 years ago
    by TinyLabs
  • Not Answered

    vldr d16, [r7, #200] ; 0xc8 causes Hard fault (Forced) 0

    5225 views
    1 reply
    Latest over 6 years ago
    by chrisc11
  • Not Answered

    How to change CM33 State from secure to non-secure 0

    • TrustZone for Armv8-M
    • Cortex-M33
    5530 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Memory related issue with MCU startup ( __libc_init_array ) +1

    • Toolchain
    • Cortex-M
    • stm32l4
    30635 views
    8 replies
    Latest over 6 years ago
    by Jacob Beningo
  • Not Answered

    STM32H7 CAN FD issues 0

    • Cortex-M7
    • stm32 h7
    • Keil
    14541 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    ADC Trigger 0

    3633 views
    1 reply
    Latest over 6 years ago
    by Andy Neil
  • Answered

    Reading ETB from software 0

    • CoreSight ETB11
    • Cortex-A9
    33247 views
    7 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Does the ThunderX CP processor support AArch32? 0

    • AArch64
    • AArch32
    20294 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    How to calculate the return address of an exception? 0

    23119 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
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