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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3657 Questions
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  • Not Answered

    To the Website admin : problem download a resticted non-confidential document 0

    22821 views
    1 reply
    Latest over 6 years ago
    by LATH
  • Not Answered

    Problems with stack pointer when i use my bootloader 0

    4942 views
    1 reply
    Latest over 6 years ago
    by JosepI
  • Not Answered

    Setting up NVIC with ISR in CortexM4 0

    7074 views
    6 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Audio Using LPC1768 (Cortex M3) 0

    5728 views
    6 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    DVFS implementation in C 0

    22308 views
    2 replies
    Latest over 6 years ago
    by Mohammed Bey
  • Answered

    EDSCR err bit set after a write to EDITR +1

    • Cortex-A57
    • AArch64
    • Armv8-A
    28030 views
    6 replies
    Latest over 6 years ago
    by kka
  • Not Answered

    Autodetect SDRAM size in uBoot Bootloader via ARMv7 processor exception handler 0

    • Armv7-A
    • Armv7 Exception Model
    25623 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Can I enable and use D-Cache with disabled MMU? 0

    31170 views
    4 replies
    Latest over 6 years ago
    by scopichmu
  • Not Answered

    cm7 and cm4 comparison 0

    3048 views
    1 reply
    Latest over 6 years ago
    by Pallavi boreddy
  • Answered

    obtaining cycle count on cortex m7 0

    8259 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    M4 Deep Sleep 0

    • STM32 F4
    6218 views
    2 replies
    Latest over 6 years ago
    by AliRizaDenenPezevenk
  • Answered

    Permission fault, level 2 on MMU enable 0

    • EL1
    • Armv8-A
    • Memory Management Unit (MMU)
    25549 views
    1 reply
    Latest over 6 years ago
    by a.surati
  • Not Answered

    Changing prio of running IRQ triggers hardfault 0

    • Armv7-M
    • Cortex-M4
    • Interrupt
    2959 views
    0 replies
    Started over 6 years ago
    by Vinci
  • Not Answered

    Cortex-M4 0

    2689 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Does MSR DAIF require ISB instruction? If no, why? 0

    • AArch64
    • Armv8-A
    26456 views
    2 replies
    Latest over 6 years ago
    by scopichmu
  • Not Answered

    Hart-i910 , what's real name of that MCU? 0

    5051 views
    3 replies
    Latest over 6 years ago
    by Andy Neil
  • Suggested Answer

    Tollchain for Cortex_M3 0

    3197 views
    1 reply
    Latest over 6 years ago
    by d.ry
  • Answered

    ACE MakeUnique Transaction 0

    22655 views
    2 replies
    Latest over 6 years ago
    by RajaAC
  • Not Answered

    What is the power consumption of a76 gpu and a77 gpu in normal state? 0

    • Cortex-A77
    • Cortex-A76
    20409 views
    0 replies
    Started over 6 years ago
    by Little_lan
  • Answered

    What can cause getting Cortex-A55 DSU P-Channel PACCEPT/PDENY signals fail? +1

    • Cortex-A55
    • Armv8-A
    • Cortex-A
    25265 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
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