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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3657 Questions
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  • Suggested Answer

    Cortex-R5F core unexpected fetch reserve address 0

    1246 views
    1 reply
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    [ARM R52+] GIC distributor on R52+ with DCLS 0

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  • Suggested Answer

    Understanding Transaction Types in ARM Systems: Real-World Applications 0

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    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Understanding the Purpose and Configuration of DAP_ROMID 0

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    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Request for Configuration and Usage Guide of PERIPH_PORT in Corinth 0

    • Cortex-A55
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  • Answered

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    Latest over 1 year ago
    by Yuping Luo Arm Employee Badge
  • Not Answered

    Cache Coherency for memory using SMMU V3 0

    • Cache coherency
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  • Suggested Answer

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    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Not Answered

    JDK 8 instructions f2xm1 and fyl2x, 80-bit extended precision implementation on ARM 0

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  • Answered

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    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Use MSI(LPIs) in Linux kernel 6.12.y 0

    1204 views
    1 reply
    Latest over 1 year ago
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  • Answered

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    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Need to get the ending address for 180 bytes of data transfer if the starting address is FFF0 and need to consider the AXI 4KB boundary. Bus width is 64 bit 0

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    Started over 1 year ago
    by Manikanta Kopparapu
  • Not Answered

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  • Answered

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    Latest over 1 year ago
    by Oliver Beirne Arm Employee Badge
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