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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3649 Questions
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  • Answered

    Can I program M95640WP using CH341A Programmer +1

    2591 views
    1 reply
    Latest over 5 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    AXI 4 Write Data Interleaving 0

    12289 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Process ADC data, moved by DMA, using CMSIS DSP: what's the right way? 0

    • Cortex-M
    • CMSIS
    • Cortex-M4
    112590 views
    44 replies
    Latest over 5 years ago
    by KyleZ
  • Not Answered

    GCC 9 stack protector comparing address of stack guard not value 0

    3863 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Booting of cortex M7 core, independently of cortex A53 core 0

    • Real Time Operating Systems (RTOS)
    • Cortex-A53
    • System on Chip (SoC)
    • Cortex-M7
    • operating systems
    3258 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    INSTRUCTION SET OF CORTEX M55? 0

    1727 views
    0 replies
    Started over 5 years ago
    by Sony
  • Not Answered

    STLink Utility Target Address 0

    1821 views
    0 replies
    Started over 5 years ago
    by JRMN
  • Answered

    Event Recorder with STM32F0 0

    • Cortex-M0
    • SRAM
    9737 views
    9 replies
    Latest over 5 years ago
    by Adam Lins
  • Answered

    Assembly code +1

    3905 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    How to test L1/L2 cache? 0

    15928 views
    2 replies
    Latest over 5 years ago
    by Zhiping Jiang
  • Not Answered

    Which bit fields are for Cortex-M4F SCB_ICSR.VECTORPENDING 0

    • Cortex-M4
    3161 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Tasks can't switch to others, always run at OSStartHang. but whitout boot code ,the app can run ok. the core of the chip is cortex-M0 +2

    9187 views
    7 replies
    Latest over 6 years ago
    by John_shi
  • Answered

    Speculative execution/loads on Cortex-A5 0

    • Cortex-A5
    • Pipeline Control and Execution
    • Cache
    16806 views
    5 replies
    Latest over 6 years ago
    by vstehle Arm Employee Badge
  • Answered

    Direct Virtual Interrupts (Timer Interrupt and IPI ) +1

    11756 views
    1 reply
    Latest over 6 years ago
    by vstehle Arm Employee Badge
  • Answered

    Inconsistent shareability domain on tlbi instructions 0

    • Cortex-A72
    • Cortex-A53
    15394 views
    3 replies
    Latest over 6 years ago
    by josecm
  • Not Answered

    Memory violation calling ATSAM3X8 0

    1779 views
    0 replies
    Started over 6 years ago
    by ccandido
  • Not Answered

    Instruction Count and Memory Access 0

    • CoreSight Debug and Trace
    • Musca-A
    • Cortex-M33
    5545 views
    2 replies
    Latest over 6 years ago
    by Lica
  • Answered

    Understanding interrupt latency and jitter in Cortex-M 0

    • Interrupt Handling
    • Cortex-M7
    • Cortex-M
    • Interrupt
    16565 views
    7 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Suggested Answer

    ARM M0 and M3 0

    3245 views
    2 replies
    Latest over 6 years ago
    by Andy Neil
  • Not Answered

    Problems with DSP course 0

    1596 views
    0 replies
    Started over 6 years ago
    by goldenthyme
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