Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Forums
Forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3657 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • TOSA forum

  • Answered

    TLB coherence expectation with TF-A running on ARM Neoverse N1 cores and CMN-600 network +1

    6800 views
    6 replies
    Latest over 5 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Microcontroller selection - Requirements and question in description 0

    • 32-bit
    • Bluetooth
    • PL351 NAND Flash Memory Controller
    • Microcontroller (MCU)
    • bluetooth 5
    • Cortex-M
    • Bluetooth LE
    • dram
    2738 views
    1 reply
    Latest over 5 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Cortex R5 Application Execution 0

    2292 views
    1 reply
    Latest over 5 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    Are there any moderators to wipe out the spam? +1

    4642 views
    3 replies
    Latest over 5 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Maybe a bug in the CMSIS library. 0

    3421 views
    6 replies
    Latest over 5 years ago
    by Andy Neil
  • Answered

    32-bit x 32-bit --->64-bit multiply +1

    • Cortex-M0
    • Cortex-M0+
    • Arm Assembly Language (ASM)
    7300 views
    5 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    SAU vs. IDAU in a System with Multiple Masters 0

    • Security
    • TrustZone
    • Armv8-M
    17588 views
    5 replies
    Latest over 5 years ago
    by Chris Reed Arm Employee Badge
  • Not Answered

    Debug single step and interrupts not executing 0

    • Interrupt Handling
    • 14 (PendSV)
    • Debugging
    • Cortex-M4
    2673 views
    0 replies
    Started over 5 years ago
    by KjO
  • Suggested Answer

    Where can I find "ARMv8 Instruction Set Overview" (PRD03-GENC-010197) 0

    • AArch64
    • Armv8-A
    7667 views
    7 replies
    Latest over 5 years ago
    by Senna van Hoek
  • Suggested Answer

    Arm Musca A1 - SRAM0 MPC Security attribute during boot 0

    • Musca-A
    • TrustZone for Armv8-M
    • CoreLink SSE-200
    6657 views
    2 replies
    Latest over 5 years ago
    by Daniel Oliveira
  • Answered

    MRAM Data Losing Problem 0

    4553 views
    5 replies
    Latest over 5 years ago
    by Andy Neil
  • Answered

    8051 cannot get serial port 1 to work +2

    • Keil C51 Dev Tools
    • C
    7624 views
    3 replies
    Latest over 5 years ago
    by Birmingham
  • Not Answered

    Cortex-M3 r2p1 TRM Document CPUID.PARTNO is wrong? 0

    2303 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    ARM Core M0 as test chip 0

    1391 views
    0 replies
    Started over 5 years ago
    by pranjal_100
  • Not Answered

    how to write interrupts function for STM32f103 in Keil 0

    2843 views
    1 reply
    Latest over 5 years ago
    by Robert McNamara
  • Answered

    Processor always jumps to default exception handler 0

    • Interrupt Handling
    • Cortex-M4
    14044 views
    13 replies
    Latest over 5 years ago
    by WestfW
  • Not Answered

    Execution stopped in EL3h mode at EL3:0x0000000000000200 +1

    • AArch64
    • Cortex-A53 FVP
    • Armv8-A
    5034 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex-M4 interrupt occures right after it's disabled 0

    3919 views
    3 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex M33 non secure wifi 0

    • Peripheral Devices
    • APB Peripherals
    • wifi
    • TrustZone
    • Cortex-M33
    1914 views
    0 replies
    Started over 5 years ago
    by beze
  • Not Answered

    AXI4 VIP unable to change values of control signal 0

    • AMBA 4
    • AXI
    • AXI4
    6151 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
<>