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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3649 Questions
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  • Not Answered

    Where I can get the TAP ID? 0

    • JTAG
    • SWD
    • Debug Access Port (DAP)
    2513 views
    1 reply
    Latest over 4 years ago
    by Annie
  • Not Answered

    Arm Atomic instructions 0

    1596 views
    1 reply
    Latest over 4 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    IO coherency 0

    2674 views
    1 reply
    Latest over 4 years ago
    by vstehle Arm Employee Badge
  • Not Answered

    In CHI spec,why normal and device memory addr aligned rule are diffrent? 0

    • CHI
    • Memory Architecture
    1407 views
    0 replies
    Started over 4 years ago
    by Furance
  • Not Answered

    R52 Development Boards +1

    • Cortex-R52
    • Development Boards
    • Software Development
    4635 views
    1 reply
    Latest over 4 years ago
    by SarahW
  • Not Answered

    STM32 F411RE SPI4 Pins Not Working 0

    2388 views
    2 replies
    Latest over 4 years ago
    by DJSG
  • Not Answered

    s802 2.0ghz mali 450 0

    1015 views
    0 replies
    Started over 4 years ago
    by squawk2003
  • Answered

    I have a question about cache operations. +1

    2508 views
    5 replies
    Latest over 4 years ago
    by YP.Lu
  • Not Answered

    Devices that Implement and Develop ARM Trustzone 0

    2262 views
    2 replies
    Latest over 4 years ago
    by Hayes169
  • Not Answered

    LDR instruction not executing 0

    • 5 (BusFault)
    • 3 (HardFault)
    • Compilers
    • Cortex-M4
    4003 views
    3 replies
    Latest over 4 years ago
    by alexxs88
  • Not Answered

    Load-Exclusive and Store-Exclusive usage confusion 0

    2179 views
    1 reply
    Latest over 4 years ago
    by Annie
  • Not Answered

    Which version of NIC support AMBA5? 0

    1626 views
    1 reply
    Latest over 4 years ago
    by Annie
  • Not Answered

    Cortex-R52 SPI interrupt routing to PEs not working 0

    2852 views
    3 replies
    Latest over 4 years ago
    by Lukas Rohrwild
  • Answered

    Enable/Disable L2 cache on ARM Cortex-A72 0

    • Cortex-A72
    4158 views
    4 replies
    Latest over 4 years ago
    by Chanh
  • Not Answered

    pl230 r0p0 dma controller 0

    1628 views
    0 replies
    Started over 4 years ago
    by Deepak Bose
  • Suggested Answer

    Set stack size in linker file for Cortex-A72 0

    3896 views
    6 replies
    Latest over 4 years ago
    by Chanh
  • Suggested Answer

    What is "AXI Ordering Model" in AXI4?? 0

    • AXI
    • AXI4
    3274 views
    1 reply
    Latest over 4 years ago
    by a.surati
  • Not Answered

    question about DAP-LITE 0

    • CoreSight Debug Access Port Lite (DAP-Lite)
    2551 views
    3 replies
    Latest over 4 years ago
    by Dibbert
  • Not Answered

    Set A72 frequency to fixed speed 0

    • Cortex-A72
    • AArch64
    • Armv8-A
    2126 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    A description of each of the pipeline stages / ARMv9 Cortex-A510 0

    3480 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
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