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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3657 Questions
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  • Not Answered

    Page tables using LPAE 0

    3121 views
    2 replies
    Latest over 3 years ago
    by jboulos
  • Answered

    GICv3: Purpose of EOIcount in ICH_HCR_EL2 and LRENPIE maintenance interrupt 0

    3978 views
    9 replies
    Latest over 3 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    memory copy using ARM NEON does not better than memcpy (a little improvement) 0

    • SIMD and Vector Execution
    3632 views
    0 replies
    Started over 3 years ago
    by soojin
  • Suggested Answer

    ARM CoreLink™︎ SMC-35x AXI Static Memory Controller Series IP 0

    • Microcontroller (MCU)
    • CoreLink SMC-35x AXI Series
    2295 views
    3 replies
    Latest over 3 years ago
    by MCU lover
  • Suggested Answer

    Is that ok to use neon instructions over vfp ? 0

    1673 views
    1 reply
    Latest over 3 years ago
    by hoover90017
  • Not Answered

    What are the most tangible differences between an SSD controller with Cortex-R8 and Cortex-R5? 0

    2266 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    ARM CoreLink™︎ SMC-35x AXI Static Memory Controller Series IP 0

    • Microcontroller (MCU)
    • Static Memory Controllers
    1514 views
    1 reply
    Latest over 3 years ago
    by MCU lover
  • Not Answered

    How does cache system work when Dual-Core Lockstep mode in Cortex-A76AE is activated. 0

    • Cortex-A76AE
    1726 views
    1 reply
    Latest over 3 years ago
    by Yiming Gan
  • Suggested Answer

    AXI5 : Read data chunking 0

    3731 views
    1 reply
    Latest over 3 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    AXI5 Atomic compare 0

    1988 views
    1 reply
    Latest over 3 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    CA55 snoop response behavior when cache line is clean 0

    1477 views
    1 reply
    Latest over 3 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Mapping MIDR PartNum to ARM Core Type 0

    3646 views
    3 replies
    Latest over 3 years ago
    by Dennis Chang
  • Not Answered

    The arm developer can't download 0

    1813 views
    2 replies
    Latest over 3 years ago
    by fish man
  • Suggested Answer

    CA55 snoop response behavior when cache line is clean 0

    2363 views
    2 replies
    Latest over 3 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Assembly encoding that triggers an exception in both the A32 and T32 instruction set 0

    1489 views
    2 replies
    Latest over 3 years ago
    by Rosario
  • Suggested Answer

    AHB5: performing a burst transfer with HBURST=SINGLE and HTRANS=NONSEQ. 0

    • AHB5
    • AHB
    3243 views
    1 reply
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    What is the difference of l3d_cache_refill and ll_cache_miss_rd? 0

    1806 views
    0 replies
    Started over 3 years ago
    by tao.wang
  • Not Answered

    The architecture definition of Speculatively executed 0

    • Architecture
    • Microarchitecture
    • Streamline Performance Analyzer
    1226 views
    0 replies
    Started over 3 years ago
    by srLeslie
  • Answered

    What role does the Activity Monitor (AMU) play in power and performance control? 0

    • Architecture
    • Armv8-A
    • Microarchitecture
    2761 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Inconsistency between the armv7-m document and physical board (B instruction, Thumb mode) 0

    • Arm Compiler
    • ARM Community
    2023 views
    1 reply
    Latest over 3 years ago
    by shenghao
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