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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3657 Questions
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  • Not Answered

    Why branch to address with LSB=0 in non-secure state will trigger secure fault? 0

    • Control Flow Instructions
    • TrustZone
    1505 views
    0 replies
    Started over 3 years ago
    by Hiilda
  • Not Answered

    Problem with a Custom IP Slave AXI 0

    • FPGA Xilinx
    • AXI4
    2659 views
    3 replies
    Latest over 3 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    M23/TrustZone - failing to write SAU and SCB_NS 0

    • Cortex-M23
    • TrustZone
    3263 views
    5 replies
    Latest over 3 years ago
    by Hiilda
  • Not Answered

    Why function's address is loaded into VMA? 0

    • Cortex-M3
    • Memory
    1289 views
    0 replies
    Started over 3 years ago
    by nmmn1359
  • Answered

    Armv9 RME Cache access and GPC sequence order 0

    5032 views
    8 replies
    Latest over 3 years ago
    by josecm
  • Not Answered

    Can you tie off TLB if you're not using virtual memory? 0

    1373 views
    1 reply
    Latest over 3 years ago
    by 42Bastian Schick
  • Suggested Answer

    Is microSCU required for multi-cores to maintain coherency? +1

    2088 views
    3 replies
    Latest over 3 years ago
    by tjones95134
  • Answered

    Cortex-A15: How to access the Revision ID register, REVIDR 0

    • Cortex-A15
    1798 views
    2 replies
    Latest over 3 years ago
    by TimF
  • Suggested Answer

    Difference in coding format. 0

    • Base ISAs
    • SIMD ISAs
    1779 views
    2 replies
    Latest over 3 years ago
    by BobP
  • Answered

    SVC instruction execution inside the hard fault handler 0

    4093 views
    4 replies
    Latest over 3 years ago
    by Sudhu145
  • Not Answered

    How to automatically detect Cortex M7 ALU overflow ?? 0

    • Interrupt Handling
    • Cortex-M7
    • Arm Compiler for Embedded FuSa
    1563 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Not Answered

    What is the unit of PMHF for R52 IP FMEDA 0

    • Cortex-R52
    962 views
    0 replies
    Started over 3 years ago
    by pengfu xie
  • Answered

    Equivalent of SSE4.2 needed for ARM support to CNDP Project 0

    3668 views
    6 replies
    Latest over 3 years ago
    by Annie
  • Not Answered

    ARMV8 arch64 how to handle bus error and interrupt occur together 0

    2543 views
    2 replies
    Latest over 3 years ago
    by Thomas Coding
  • Not Answered

    Cortex-M7 Failing to read PPB ROM table 0

    1203 views
    0 replies
    Started over 3 years ago
    by Bert Hindle
  • Not Answered

    Debug Print Logs Display and Hardware Power Issue in KEIL uVision 5 (Cortex-M0) 0

    1636 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Not Answered

    SMMUv2 IRQS per Context Bank 0

    • SMMUv2
    915 views
    0 replies
    Started over 3 years ago
    by Jorge
  • Not Answered

    The pipeline of add with lsl >4 in Neoverse N1 0

    • Documentation
    • Neoverse N1
    1145 views
    0 replies
    Started over 3 years ago
    by Juneyoung Lee
  • Not Answered

    Can I use a Single Linux OS to schedule two DSU cluster? 0

    • Embedded Linux
    • DynamIQ
    2900 views
    3 replies
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    Enabling MPU causes clearing of Stack in Cortex R5F 0

    • Cortex-R5
    1791 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
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