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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3657 Questions
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  • Answered

    Cortex-X : Next generation 0

    2189 views
    2 replies
    Latest over 2 years ago
    by Jerome Decamps - 杜尚杰
  • Not Answered

    Cortex-v7M MPU reprogramming 0

    1471 views
    0 replies
    Started over 2 years ago
    by amk
  • Not Answered

    [Cortex-A15/Arm7v]Is the way to disable the speculative memory accesses of L1 0

    • Cortex-A15
    2887 views
    4 replies
    Latest over 2 years ago
    by Y.Im
  • Not Answered

    Using SSE-200 MPU to modify specific region from normal to device memory 0

    1014 views
    0 replies
    Started over 2 years ago
    by SarahW
  • Not Answered

    Cotex M4 + FreeRTOS -- CPU register cleared after wfi/sleep mode 0

    • Cortex-M4
    • STM32 F3
    2064 views
    0 replies
    Started over 2 years ago
    by Martin Wagner
  • Answered

    LDR (literal) instruction VR Field meaning 0

    • Memory Access Instructions
    2875 views
    2 replies
    Latest over 2 years ago
    by ADJ
  • Not Answered

    Instruction fetch alignment 0

    • Cortex-A
    • Instruction Fetch
    1521 views
    0 replies
    Started over 2 years ago
    by rkd
  • Suggested Answer

    could the Rready signal be asynchronous with aclk? 0

    1391 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Atomic transaction AMBA 5 0

    2172 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    RAS Fault injection on A78AE 0

    • Cortex-A78AE
    1088 views
    0 replies
    Started over 2 years ago
    by irodrigu
  • Not Answered

    A53 latencies / jitter (memory access)? 0

    • Cortex-A53
    • Memory
    1558 views
    0 replies
    Started over 2 years ago
    by linuxonarm
  • Answered

    Estimate timing cycle of udiv instruction. 0

    • Cortex-M4
    3626 views
    3 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Cortex M55 - peripheral access using AXI instead of AHB 0

    • Cortex-M55
    2837 views
    1 reply
    Latest over 2 years ago
    by Toshihisa Oishi Arm Employee Badge
  • Answered

    Difference between CPU architecture and ISA 0

    • Learn the Architecture
    5060 views
    4 replies
    Latest over 2 years ago
    by Kaze
  • Answered

    What is the purpose of the coprocessor interface in Cortex-M series and how to use it? 0

    • Cortex-R
    • Cortex-M
    3415 views
    3 replies
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Inquire about the official DMIPS/MHz value for Cortex A53. 0

    • Cortex-A53
    4944 views
    0 replies
    Started over 2 years ago
    by daehyunyoon
  • Suggested Answer

    How many cycles will CYCCNT count during CPU halt? 0

    2075 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Cacheable=0 vs Shareable=1 0

    • Cache coherency
    • Cortex-R5
    • Memory Protection Unit (MPU)
    3049 views
    2 replies
    Latest over 2 years ago
    by AakashKedia22
  • Suggested Answer

    Cortex R52+ typical interrupt latencies 0

    1864 views
    1 reply
    Latest over 2 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Cortex X4/A720/A520 optimization guides? 0

    3784 views
    1 reply
    Latest over 2 years ago
    by George Steed Arm Employee Badge
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