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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3657 Questions
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  • Answered

    SWD for Time Profiling if no ETM Time Stamping is available +1

    • Profiling
    • Trace Debug Tools (TDT)
    • Debugger
    • Cortex-M4
    3663 views
    1 reply
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    SWD for Time Profiling if no ETM Time Stamping is available 0

    • Real-Time
    • Trace Debug Tools (TDT)
    • Debugging
    • Cortex-M4
    13301 views
    0 replies
    Started over 7 years ago
    by Andrea Bettati
  • Not Answered

    Non-secure code calling secure code - Boot Loaders 0

    10771 views
    2 replies
    Latest over 7 years ago
    by vinkot Arm Employee Badge
  • Answered

    Count Main TLB miss +1

    • Cortex-A9
    • performance analysis
    15493 views
    1 reply
    Latest over 7 years ago
    by Vanhealsing
  • Answered

    Interrupts in assembly language +1

    • Microcontroller (MCU)
    • Interrupt
    14422 views
    1 reply
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    The Peripherals memory map of FVP_BaseR_Cortex-R52x1 0

    • Cortex-R52
    • Fixed Virtual Platforms (FVPs)
    • PrimeCell UART (PL011)
    2837 views
    0 replies
    Started over 7 years ago
    by Jex1x
  • Answered

    Basic difference between "Generic User Guide" and "Technical Reference Manual" +1

    • Cortex-M0+
    17134 views
    1 reply
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    VMSAv8-64 and spinlock +1

    • Cortex-A53
    • Cache coherency
    • Cortex-A
    • Baremetal
    17409 views
    3 replies
    Latest over 7 years ago
    by Ciro Donnarumma
  • Answered

    A question aboout Monitor Vector Base Address Register(MVBAR) 0

    • Cortex-A9
    • TrustZone
    18119 views
    6 replies
    Latest over 7 years ago
    by scribnote5
  • Answered

    SysTick 0

    • 15 (SysTick)
    4140 views
    1 reply
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    shareable domain and cache policy problem 0

    • Cortex-A53
    • big.LITTLE
    • L1
    • Cache
    • Cortex-A
    • L2
    12953 views
    0 replies
    Started over 7 years ago
    by zhi
  • Answered

    Configuring an interrupt source as FIQ at EL1 +1

    • Cortex-A53
    • GICv2
    • Kernel Developers
    17889 views
    2 replies
    Latest over 7 years ago
    by Sumit Batra
  • Answered

    MMU initialization for an ARM multicore system +1

    • Cortex-A9
    • Memory Management Unit (MMU)
    • Cortex-A
    • Baremetal
    • Memory
    21948 views
    6 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Why NSCAR(Non-secure Access Control Register) changes often? 0

    • Cortex-A9
    • Registers
    • TrustZone
    15437 views
    4 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    stm32f103c8t6 "blue pill" board +1

    • Cortex-M3
    • IDEs and Tool Suites
    • Cortex-M
    4658 views
    1 reply
    Latest over 7 years ago
    by chrisKConti
  • Not Answered

    NMI Handling in Bootloader +1

    • 2 (NMI)
    • Cortex-M
    5125 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    How can I get the number of non-cacheable access in CA-55? 0

    • Cortex-A55
    12141 views
    0 replies
    Started over 7 years ago
    by Hyunjong
  • Answered

    dump MMU translation table for A9 in Linux +1

    • Cortex-A9
    • Embedded Linux
    • Memory Management Unit (MMU)
    • Cortex-A
    17051 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    How to use Secure Monitor Call(SMC) and entrance Monitor Mode? 0

    • Cortex-A9
    • TrustZone
    15575 views
    1 reply
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    c register config 0

    • Cortex-M7
    • Cortex-M
    4924 views
    4 replies
    Latest over 7 years ago
    by Rajeswari Pallagani
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