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Forums

  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 10 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    717 questions
    Antonios Kekempanos
    RE: Error Synthesizing Design Start ARM Cortex M3 on Xilinx FPGA 6 days ago
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 9 months ago Arm Employee Badge
  • TOSA forum

    Tensor Operator Set Architecture (TOSA) provides a set of whole-tensor operations commonly employed by Deep Neural Networks.
    1 question
    Oliver Beirne
    RE: Forum FAQs 4 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 10 years ago Arm Employee Badge
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All questions in this Community
  • Answered

    Keil V4.03 +1

    1802 views
    1 reply
    Latest over 1 year ago
    by rkopsch Arm Employee Badge
  • Not Answered

    8051 C compiler and a while-loop 0

    655 views
    0 replies
    Started over 1 year ago
    by clauswk
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    Inquire about the official DMIPS/MHz value for Cortex A53. 0

    • Cortex-A53
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    0 replies
    Started over 1 year ago
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  • Answered

    About Mali GPU index buffer processing (group of 4 indices) +1

    • GPU Architecture
    • optimization
    • Optimization Solution
    • Mali GPUs
    • gpu
    2364 views
    1 reply
    Latest over 1 year ago
    by Peter Harris Arm Employee Badge
  • Suggested Answer

    Hi I need help with enabling/disabling process if mmu and mpu in cortex r5 and cortex a53 so that two processor application variable cant access each other memory address value and modify them 0

    2516 views
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    Latest over 1 year ago
    by nit_001
  • Suggested Answer

    How many cycles will CYCCNT count during CPU halt? 0

    1695 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    How to auto-vectorize fp16 loop under arm sve? 0

    • LLVM
    • GCC
    • Vectorization
    896 views
    0 replies
    Started over 1 year ago
    by yiwang
  • Answered

    Cacheable=0 vs Shareable=1 0

    • Cache coherency
    • Cortex-R5
    • Memory Protection Unit (MPU)
    2378 views
    2 replies
    Latest over 1 year ago
    by AakashKedia22
  • Suggested Answer

    Filesystem is corrupted when sharing files from host to the Virtual Platform 0

    3817 views
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    How to implement matrix multiplication and addition operations by operating the Ethos-u65 register 0

    • Ethos-U65
    • microNPU
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    Started over 1 year ago
    by iStarChip
  • Suggested Answer

    Problems with adding breakpoints in KEIL 0

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    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
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    Compiler 5 license error 0

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    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    question related to AxREGION in AXI 0

    1043 views
    0 replies
    Started over 1 year ago
    by Harekrishna
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    Exclusive Access In AXI3/4/5 0

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    Started over 1 year ago
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    Atomic transaction AMBA 5 0

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