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Forums

  • Operating Systems forum

    The latest forum discussions for all Arm technology relating to Operating Systems (OS)
    272 questions
    Cantaff0rd
    UEFI variables from UEFI shell 2 months ago
  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 5 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    707 questions
    Firoz M L
    In CHI how the Slave side is giving the L-Credits to the Master Side 2 days ago
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 4 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 9 years ago Arm Employee Badge
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All questions in this Community
  • Not Answered

    Arm Cortex M7 SWD (Serial Wire Debug) read DPACC DPIDCODE failed 0

    • DPACC
    • Cortex M7
    • SWD
    814 views
    0 replies
    Started over 1 year ago
    by Hsu HANWENHSU
  • Answered

    "Unknown signal" when trace GPIO pin status in Keil5 logic analyzer (Nucleo-H743ZI2) +1

    • Keil MDK
    2448 views
    3 replies
    Latest over 1 year ago
    by Andreas B.
  • Answered

    Cortex M7 can't issue 0xF0000000 address +1

    • Cortex M7
    1451 views
    2 replies
    Latest over 1 year ago
    by Hsu HANWENHSU
  • Not Answered

    Can I Access Cacheable Areas with Data Cache Disabled? 0

    • Cache
    • Cache Management
    • Memory Management Unit (MMU)
    1370 views
    2 replies
    Latest over 1 year ago
    by User_0182
  • Answered

    Some questions about MSAA on mali-G77 0

    • Valhall
    • Android
    • G77
    • vulkan
    • performance
    • msaa
    • Streamline
    • Mali-GPU
    4286 views
    7 replies
    Latest over 1 year ago
    by yonghao lu
  • Suggested Answer

    RAS Error injection(DE/CE) and containment on Cortex-A 0

    • Error Injection
    • ERR0PFGCTL
    • RAS
    • Cortex-A
    2325 views
    3 replies
    Latest over 1 year ago
    by Michael Williams Arm Employee Badge
  • Answered

    How does one disable warnings during the build process in Keil 5 ? 0

    879 views
    2 replies
    Latest over 1 year ago
    by Abraxas
  • Not Answered

    Generating a custom software package for third part in Keil MDK 0

    • Package management
    • Keil MDK
    • Library and Special Function Routines
    • Library
    890 views
    2 replies
    Latest over 1 year ago
    by Alessandro Manfredi
  • Not Answered

    How can I check the number of multi-core in keil? 0

    • Keil
    373 views
    0 replies
    Started over 1 year ago
    by MONG
  • Answered

    Why does the APB bus need a PENABLE signal? 0

    • APB Peripherals
    • AMBA 3 APB Interface
    • AMBA 2 APB Interface
    2743 views
    2 replies
    Latest over 1 year ago
    by Arseniy Antonyuk
  • Not Answered

    Regarding the order of interrupt requests 0

    • Interrupt Handling
    • Cortex-M4
    637 views
    0 replies
    Started over 1 year ago
    by Makoto Satou
  • Suggested Answer

    Any chance to share the LDPC sample ? 0

    • ArmRAL
    1925 views
    1 reply
    Latest over 1 year ago
    by Chris Goodyer Arm Employee Badge
  • Suggested Answer

    Failed to launch debug server - rddidap_serverd 0

    • rddidap_serverd
    3074 views
    5 replies
    Latest over 1 year ago
    by Stephen Theobald Arm Employee Badge
  • Answered

    Is Arm Core PMU and DSU_PMU the same hardware component? 0

    • DSU-120
    • Cortex-A
    • pmu-dsu
    • Cortex-A720
    1317 views
    1 reply
    Latest over 1 year ago
    by Michael Williams Arm Employee Badge
  • Suggested Answer

    How does the Cortex M0+ pipeline handle a branch instruction to an address that is not 32-bit aligned? 0

    • Pipeline Control and Execution
    • Cortex-M0+
    1422 views
    1 reply
    Latest over 1 year ago
    by Mahmood Yakub Arm Employee Badge
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