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Operating Systems forum
The latest forum discussions for all Arm technology relating to Operating Systems (OS)
272
questions
UEFI variables from UEFI shell
3 months ago
Servers and Cloud Computing forum
The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
101
questions
RE: ArmRAL: Wrong usage of k0 in LDPC rate matching
6 months ago
SoC Design and Simulation forum
The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
707
questions
In CHI how the Slave side is giving the L-Credits to the Master Side
11 days ago
SystemReady Forum
The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
15
questions
RE: How to run ARM ACS
4 months ago
恩智浦汽车电子MCU讨论区博
4
questions
RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼
over 9 years ago
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Not Answered
ARM: Specifying callers of indirect function calls for --callgraph option
0
Keil MDK
799
views
0
replies
Started
over 6 years ago
by
David Martin
Not Answered
Use __attribute__ Error L6406E, L6407E
0
Keil MDK
3562
views
1
reply
Latest
over 6 years ago
by
Andrew Neil
Not Answered
How to set the const variable I want in the last position of FLASH
0
Keil MDK
1956
views
2
replies
Latest
over 6 years ago
by
Westonsupermare Pier
Not Answered
Issues with VLA and Keil
0
Microcontroller (MCU)
1900
views
3
replies
Latest
over 6 years ago
by
Dave Crabs
Not Answered
DS-5 ignores dependencies for assembly files.
0
Arm Compiler 6
DS-5 Ultimate Edition
DS-5 Community Edition
15669
views
1
reply
Latest
over 6 years ago
by
Nick S.
Answered
aarch64 Exception Level Sw itch from EL1 to EL0
0
EL1
EL3
AArch64
Raspberry Pi 3
EL0
QEMU
Cortex-A
16836
views
7
replies
Latest
over 6 years ago
by
michaelyuanfeng
Suggested Answer
How to handle clean operation in Data Cache
0
Cache coherency
18980
views
1
reply
Latest
over 6 years ago
by
Christopher Tory
Suggested Answer
How to handle Cache flush in ACE?
0
AMBA
ACE
Cache
Interface
16885
views
1
reply
Latest
over 6 years ago
by
Christopher Tory
Not Answered
when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thanks a lot!
0
Cortex-A53
Cache
Cortex-A
Memory
9910
views
0
replies
Started
over 6 years ago
by
sam0220
Not Answered
Development Boards for ML Processor
0
machine learning
Neural Network
Internet of Things (IoT)
6598
views
2
replies
Latest
over 6 years ago
by
Jason Andrews
Not Answered
ldr and fmla instruction time consumption issue.
0
19526
views
8
replies
Latest
over 6 years ago
by
arthur_libin
Answered
MMU and Cache configuration
0
Cortex-A5
Cache
Memory Management Unit (MMU)
Cortex-A
23860
views
12
replies
Latest
over 6 years ago
by
Vanhealsing
Answered
Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification
+1
AMBA
AHB5
AMBA 5
AHB
13840
views
1
reply
Latest
over 6 years ago
by
Colin Campbell
Not Answered
Cannot find definition of extern function, reference only
0
Microcontroller (MCU)
2743
views
3
replies
Latest
over 6 years ago
by
Andrew Neil
Not Answered
aarch64 MMU: inconsistency in ARMv8 ARM?
0
logic
Armv8-A
Memory Management Unit (MMU)
Memory Management
14728
views
1
reply
Latest
over 6 years ago
by
Zhifei Yang
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