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Forums

  • Operating Systems forum

    The latest forum discussions for all Arm technology relating to Operating Systems (OS)
    272 questions
    Cantaff0rd
    UEFI variables from UEFI shell 2 months ago
  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 5 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    705 questions
    Rishi Cheriyan
    Compatibility of PWAKEUP of APB completer with Q-channel compliant clock controller 6 days ago
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 4 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 9 years ago Arm Employee Badge
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All questions in this Community
  • Answered

    Question about low-cost Chinese STM32H750 boards from Ebay, Alibaba, etc. +1

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    by Andy Neil
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    • Cortex-M0
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    • Keil C51 Dev Tools
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    How to access memory more than 4GB by using 32bit ISA? +1

    • Memory Access Instructions
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    4 replies
    Latest over 5 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

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    by Alexandraanderson
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    Started over 5 years ago
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    • Cortex-R52
    • Arm Development Studio
    • GICv3/v4
    • Generic Interupt Controller
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    making physical memory pages not cacheable (probabaly by modifying page table entry) 0

    20358 views
    0 replies
    Started over 5 years ago
    by Gol
  • Not Answered

    Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore 0

    • System on Chip (SoC)
    • Cortex-A9
    22316 views
    3 replies
    Latest over 5 years ago
    by BurakSeker
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