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Forums

  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 10 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    717 questions
    Antonios Kekempanos
    RE: Error Synthesizing Design Start ARM Cortex M3 on Xilinx FPGA 2 days ago
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 9 months ago Arm Employee Badge
  • TOSA forum

    Tensor Operator Set Architecture (TOSA) provides a set of whole-tensor operations commonly employed by Deep Neural Networks.
    1 question
    Oliver Beirne
    RE: Forum FAQs 4 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 10 years ago Arm Employee Badge
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All questions in this Community
  • Not Answered

    SOC sensor chips 0

    408 views
    0 replies
    Started 10 months ago
    by Brahm
  • Suggested Answer

    Difference between System mode, User mode and Supervisor mode in Cortex R. 0

    • Cortex R
    1648 views
    1 reply
    Latest 10 months ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Can a WriteUnique be sent after CompDBIDResp but before CopybackWrData? 0

    • AMBA 5 CHI
    • CHI
    1434 views
    1 reply
    Latest 10 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Understanding Correspondence of 1-bit ACTIVE Signal to Different Power Modes in Arm®︎ Power Policy Unit Architecture Specification 0

    • PPU
    • q-channel
    2022 views
    3 replies
    Latest 10 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Cortex-R5F core unexpected fetch reserve address 0

    927 views
    1 reply
    Latest 10 months ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    [ARM R52+] GIC distributor on R52+ with DCLS 0

    • GICv3/v4
    • Armv8-R
    1102 views
    2 replies
    Latest 10 months ago
    by ShihHsun Chang
  • Not Answered

    Next execution statement not working in debug mode when using step into button 0

    • Keil
    967 views
    2 replies
    Latest 10 months ago
    by himanshu mehta
  • Not Answered

    Question about ITS Retry Behavior after Stalled MAPD Command 0

    1027 views
    2 replies
    Latest 10 months ago
    by steve jeong
  • Answered

    Streamline annotation reset counter 0

    1841 views
    3 replies
    Latest 10 months ago
    by Peter Harris Arm Employee Badge
  • Answered

    ArmRAL: Wrong usage of k0 in LDPC rate matching 0

    • ArmRAL
    2265 views
    2 replies
    Latest 10 months ago
    by romain beurdouche
  • Suggested Answer

    I'm curious about how INTID calculation works. 0

    • GIC400
    • INTID
    1337 views
    1 reply
    Latest 10 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    AXI4 ordering Model. 0

    • AXI4
    1171 views
    1 reply
    Latest 10 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Understanding Transaction Types in ARM Systems: Real-World Applications 0

    • ACE
    1138 views
    1 reply
    Latest 10 months ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Understanding the Purpose and Configuration of DAP_ROMID 0

    • Cortex-R5
    2274 views
    6 replies
    Latest 10 months ago
    by ele
  • Suggested Answer

    Mali-G715-Immortalis MC11 r1p2 slower than mali G72 MC24 0

    6841 views
    14 replies
    Latest 10 months ago
    by hterrolle
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