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Operating Systems forum
The latest forum discussions for all Arm technology relating to Operating Systems (OS)
272
questions
UEFI variables from UEFI shell
3 months ago
Servers and Cloud Computing forum
The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
101
questions
RE: ArmRAL: Wrong usage of k0 in LDPC rate matching
5 months ago
SoC Design and Simulation forum
The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
707
questions
In CHI how the Slave side is giving the L-Credits to the Master Side
10 days ago
SystemReady Forum
The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
15
questions
RE: How to run ARM ACS
4 months ago
恩智浦汽车电子MCU讨论区博
4
questions
RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼
over 9 years ago
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ShenZhen Hao Qi Core Technology Analysis: What are the techniques for chip decryption?
0
1756
views
1
reply
Latest
over 3 years ago
by
vinniesenger
Answered
Migrate from Keil 4 to 5 issue
+1
Keil MDK
1984
views
9
replies
Latest
over 3 years ago
by
Grant B
Answered
Keil RTX, isn't osDelay accurate?
+1
2149
views
3
replies
Latest
over 3 years ago
by
Robert McNamara
Answered
"Unable to execute remote query" issue
0
License Management
4306
views
13
replies
Latest
over 3 years ago
by
xiaoyuan
Suggested Answer
Define AEM-A core on configuration database ARM DS
0
1809
views
1
reply
Latest
over 3 years ago
by
Ronan Synnott
Answered
Qualcomm 888/Cortex-X1 profiling
+1
CPU Architecture
A-Profile CPU
Mobile computing
Cortex-A55
Hardware Development Tools
Hardware Probes
Development Boards
Arm Mobile Studio
Cortex-A78
10406
views
16
replies
Latest
over 3 years ago
by
torvik
Answered
Possible allocatable RAM memory for A53 mode
+2
1359
views
3
replies
Latest
over 3 years ago
by
Stephen Theobald
Answered
In ARM Cortex R5 TRM, Number of MPU region is stated as 12 or 16 in MPU chapter and 8 and 12 in chapter 2. Which one is correct?
0
Cortex-R5
Armv7-R
1670
views
2
replies
Latest
over 3 years ago
by
Buvanesh
Answered
Senseless send CAN frame
0
Communications Standards
driver
969
views
2
replies
Latest
over 3 years ago
by
Rémi G
Answered
RA2E2 Setting the Options Function Select Register in Assembly
0
594
views
1
reply
Latest
over 3 years ago
by
Sascha2210
Suggested Answer
About the difference between the terms l3_cache and ll_cache
0
Cache Controllers
Cache Architecture
2062
views
1
reply
Latest
over 3 years ago
by
Eugene Choi
Answered
Expression With Possibly No Effect
+1
1764
views
1
reply
Latest
over 3 years ago
by
rkopsch
Answered
Can Cortex A8 NEON optimized code work on Cortex A5 NEON?
0
2583
views
6
replies
Latest
over 3 years ago
by
zhongl
Answered
Project management - targets with same file names in different paths
0
982
views
1
reply
Latest
over 3 years ago
by
ChenTang
Not Answered
LPC1768 two pin ADC
0
695
views
0
replies
Started
over 3 years ago
by
sajaddehghan
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