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Forums

  • Operating Systems forum

    The latest forum discussions for all Arm technology relating to Operating Systems (OS)
    272 questions
    Cantaff0rd
    UEFI variables from UEFI shell 3 months ago
  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 5 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    707 questions
    Firoz M L
    In CHI how the Slave side is giving the L-Credits to the Master Side 7 days ago
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 4 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 9 years ago Arm Employee Badge
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All questions in this Community
  • Suggested Answer

    Disassembly on Debug 0

    • Debugging
    708 views
    1 reply
    Latest over 2 years ago
    by WestfW
  • Answered

    OpenCL profiling for Mali GPU +1

    • OpenCL
    • arm streamline
    • Arm Profiler
    9008 views
    7 replies
    Latest over 2 years ago
    by ran_guo
  • Answered

    Download errors when trying to download a legacy compiler for Keil +1

    • Keil MDK
    • Legacy products
    • University and Research
    • Arm Compiler 5
    • Legacy compilers
    3124 views
    3 replies
    Latest over 2 years ago
    by rkopsch Arm Employee Badge
  • Not Answered

    ARM CoreLink™︎ SMC-35x AXI Static Memory Controller Series IP 0

    • Microcontroller (MCU)
    • Static Memory Controllers
    1259 views
    1 reply
    Latest over 2 years ago
    by MCU lover
  • Not Answered

    How does cache system work when Dual-Core Lockstep mode in Cortex-A76AE is activated. 0

    • Cortex-A76AE
    1332 views
    1 reply
    Latest over 2 years ago
    by Yiming Gan
  • Suggested Answer

    AXI5 : Read data chunking 0

    2723 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    AXI5 Atomic compare 0

    1519 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    CA55 snoop response behavior when cache line is clean 0

    1072 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    In CHI spec, if the Requester initial state is UD or SD, what the final cache state of a ReadClean transaction should be? +1

    2629 views
    1 reply
    Latest over 2 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Build logs for ARM GNU toolchain 0

    • Cross compiling
    • Cross-platform tools
    528 views
    0 replies
    Started over 2 years ago
    by afs 2023
  • Answered

    Improvement to RTE_Components.h +1

    2096 views
    4 replies
    Latest over 2 years ago
    by rkopsch Arm Employee Badge
  • Not Answered

    Cortex M4 core simulator , Simulation in MDK-ARM? 0

    842 views
    0 replies
    Started over 2 years ago
    by HansB
  • Answered

    Total number of Texture requests on G78 / G710 +1

    1820 views
    1 reply
    Latest over 2 years ago
    by Peter Harris Arm Employee Badge
  • Not Answered

    Windows C++ ARM CPU detection in user mode 0

    • Windows 10
    3328 views
    1 reply
    Latest over 2 years ago
    by Lucas Mulling
  • Answered

    Mapping MIDR PartNum to ARM Core Type 0

    2537 views
    3 replies
    Latest over 2 years ago
    by Dennis Chang
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