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Forums

  • Operating Systems forum

    The latest forum discussions for all Arm technology relating to Operating Systems (OS)
    273 questions
    Oliver Beirne
    This forum is now read-only. Learn more here. 1 month ago Arm Employee Badge
  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    103 questions
    Oliver Beirne
    RE: Using GitHub with Arm? (2-minute survey) 5 months ago Arm Employee Badge
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    729 questions
    Colin Campbell
    RE: Does AHB Specification prohibit a combo path from HTRANS to HREADYOUT? 3 days ago Arm Employee Badge
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS over 1 year ago Arm Employee Badge
  • TOSA forum

    Tensor Operator Set Architecture (TOSA) provides a set of whole-tensor operations commonly employed by Deep Neural Networks.
    1 question
    Oliver Beirne
    RE: Forum FAQs 11 months ago Arm Employee Badge
  • 一般讨论和通告

    1 question or discussion
    Fei Xiang
    论坛常见问题(FAQ) 6 months ago Arm Employee Badge
  • 云计算

    1 question or discussion
    Fei Xiang
    论坛常见问题(FAQ) 6 months ago Arm Employee Badge
  • 人工智能与机器学习

    1 question or discussion
    Fei Xiang
    论坛常见问题(FAQ) 6 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 10 years ago Arm Employee Badge
  • 机器人和具身智能

    1 question or discussion
    Fei Xiang
    论坛常见问题(FAQ) 6 months ago Arm Employee Badge
  • 汽车和自动驾驶

    1 question or discussion
    Fei Xiang
    论坛常见问题(FAQ) 6 months ago Arm Employee Badge
  • 游戏和图形技术

    2 questions and discussions
    Fei Xiang
    论坛常见问题(FAQ) 6 months ago Arm Employee Badge
  • 物联网

    1 question or discussion
    Fei Xiang
    论坛常见问题(FAQ) 6 months ago Arm Employee Badge
  • 移动端应用开发

    1 question or discussion
    Fei Xiang
    论坛常见问题(FAQ) 6 months ago Arm Employee Badge
  • 笔记本电脑

    1 question or discussion
    Fei Xiang
    论坛常见问题(FAQ) 6 months ago Arm Employee Badge
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All questions in this Community
  • Answered

    why it apperars an CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST error when read buffer from gpu back to host memory? +1

    • OpenCL
    • Mali-T760
    • Mali-GPU
    12881 views
    8 replies
    Latest over 11 years ago
    by Anthony Barbier Arm Employee Badge
  • Not Answered

    Regarding ADFSR and AIFSR in ARM Cortex-A9 MPcore 0

    • Cortex-A9
    • Cortex-A
    4956 views
    2 replies
    Latest over 11 years ago
    by Niranjan Dighe
  • Answered

    In cortex-A7 it has 8 stages pipeline, so PC's value is current program address add how many? 0

    • Cortex-A
    • Cortex-A7
    4825 views
    1 reply
    Latest over 11 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Saving in 8051 IDATA starting from 92H 0

    • Keil C51 Tools
    4402 views
    11 replies
    Latest over 11 years ago
    by Andy Neil
  • Answered

    clean and invalidate cache behavior before same address read +1

    • Cortex-A17
    • Cortex-A
    6564 views
    4 replies
    Latest over 11 years ago
    by loquat
  • Answered

    I2S with ARM M0 +1

    • Cortex-M0
    • Cortex-M
    8959 views
    3 replies
    Latest over 11 years ago
    by daith
  • Not Answered

    setting keil/mdk include folders really bothers 0

    • Keil MDK
    6554 views
    7 replies
    Latest over 11 years ago
    by HansBernhard Broeker
  • Answered

    Where can I find the cortex-A7 related 8 stages pipeline docments? 0

    • Cortex-A
    • Cortex-A7
    4836 views
    2 replies
    Latest over 11 years ago
    by Kun.Niu
  • Answered

    If a region is marked as non-cacheable, will the CPU also first check the cache when CPU want to access the region? 0

    • Cortex-A
    • Cortex-A7
    5237 views
    1 reply
    Latest over 11 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    In USB why VID(vendor id) , PID(Product id ) are required?? +1

    • Cortex-M
    26723 views
    5 replies
    Latest over 11 years ago
    by Mustafa S.
  • Answered

    Questions about Generic Timer in ARMv8 0

    • big.LITTLE
    • Armv7-A
    • Cortex-A9
    • Cortex-A15
    • Cortex-A
    • Cortex-A7
    11332 views
    4 replies
    Latest over 11 years ago
    by wangchj
  • Answered

    Break Points and Watch Points +1

    • Armv7-M
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    5808 views
    1 reply
    Latest over 11 years ago
    by Mustafa S.
  • Not Answered

    bin file 0

    • Keil C51 Tools
    3711 views
    13 replies
    Latest over 11 years ago
    by Cottan Bud
  • Not Answered

    filesystem accessed by multiple threads 0

    • Keil MDK
    1520 views
    3 replies
    Latest over 11 years ago
    by ImPer Westermark
  • Not Answered

    what are the advantages of 8051 over other microcontrollers for example ARM, Ardino,PIC etc 0

    • Keil C51 Tools
    5612 views
    10 replies
    Latest over 11 years ago
    by John Linq
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