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Forums

  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 10 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    717 questions
    Antonios Kekempanos
    RE: Error Synthesizing Design Start ARM Cortex M3 on Xilinx FPGA 18 days ago
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 9 months ago Arm Employee Badge
  • TOSA forum

    Tensor Operator Set Architecture (TOSA) provides a set of whole-tensor operations commonly employed by Deep Neural Networks.
    1 question
    Oliver Beirne
    RE: Forum FAQs 5 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 10 years ago Arm Employee Badge
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All questions in this Community
  • Answered

    upgrade from C51 IDE version 4.5 to the latest +1

    1124 views
    1 reply
    Latest over 1 year ago
    by rkopsch Arm Employee Badge
  • Answered

    Incorrect rendering result on a fragment shader with bitwise not operation +1

    • Mali Drivers
    • OpenGL ES
    • Mali-GPU
    2982 views
    4 replies
    Latest over 1 year ago
    by Kloten Bach
  • Answered

    printf formatting example 0

    1802 views
    2 replies
    Latest over 1 year ago
    by Fausto Bartra
  • Not Answered

    keil uversion options for traget for mspm0g3507 from Ti 0

    1345 views
    1 reply
    Latest over 1 year ago
    by Annie
  • Suggested Answer

    how to reset axi master can cause axi bus deadlock in soc design 0

    1726 views
    1 reply
    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Reboot failing in FVP RDV2 platform +1

    • rdv2
    • tf-a
    • fvp
    • Neoverse Reference Design
    1749 views
    2 replies
    Latest over 1 year ago
    by Toshihisa Oishi Arm Employee Badge
  • Not Answered

    armgcc 13.2.1 optimization issue 0

    • GNU Arm Embedded Toolchain
    • optimization
    757 views
    0 replies
    Started over 1 year ago
    by Jason Yu
  • Not Answered

    An interruption occurs in all socket connections when a socket connection is disrupted(TCP and BSD) 0

    • TCP
    • STM32 F1
    • BSD Networking
    1058 views
    1 reply
    Latest over 1 year ago
    by Franc Urbanc Arm Employee Badge
  • Suggested Answer

    Load hex instead of axf 0

    • uVision
    • STM32
    1352 views
    1 reply
    Latest over 1 year ago
    by Milorad Cvjetkovic Arm Employee Badge
  • Suggested Answer

    The bare metal program got stuck at some point. 0

    • AArch64
    • U-Boot
    1649 views
    1 reply
    Latest over 1 year ago
    by Stephen Theobald Arm Employee Badge
  • Not Answered

    GPIO manipulation on A55 core of IMX93 with JTAG 0

    • JTAG
    • Cortex-A55
    • GPIO
    • uboot
    • secure
    1579 views
    0 replies
    Started over 1 year ago
    by Adam Honeybell
  • Answered

    no TRACE available when debugger is an CMSIS-DAP Debugger (MCU link) +1

    2688 views
    4 replies
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    Startup files for MK10DN128xxx5 NXP MCUs 0

    896 views
    1 reply
    Latest over 1 year ago
    by Stephen Theobald Arm Employee Badge
  • Not Answered

    Lora SX1278 with STM32F1C308 is not running (using KeilC u5 and Standard Peripheral Library). I can't write and read command to Lora register. Please someone help me. 0

    923 views
    1 reply
    Latest over 1 year ago
    by Annie
  • Not Answered

    Relationship between ARM's shareability domain, cache maintenance and barrier 0

    • Cache coherency
    • Armv8-A
    • barrier
    • memory-model
    • Cache Architecture
    • Memory Management
    2112 views
    2 replies
    Latest over 1 year ago
    by Joon Kang
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