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Operating Systems forum
The latest forum discussions for all Arm technology relating to Operating Systems (OS)
273
questions
This forum is now read-only. Learn more here.
17 days ago
Servers and Cloud Computing forum
The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
103
questions
RE: Using GitHub with Arm? (2-minute survey)
4 months ago
SoC Design and Simulation forum
The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
729
questions
RE: Does AHB Specification prohibit a combo path from HTRANS to HREADYOUT?
11 days ago
SystemReady Forum
The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
15
questions
RE: How to run ARM ACS
over 1 year ago
TOSA forum
Tensor Operator Set Architecture (TOSA) provides a set of whole-tensor operations commonly employed by Deep Neural Networks.
1
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RE: Forum FAQs
10 months ago
一般讨论和通告
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5 months ago
云计算
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5 months ago
人工智能与机器学习
1
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5 months ago
恩智浦汽车电子MCU讨论区博
4
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RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼
over 10 years ago
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5 months ago
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5 months ago
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5 months ago
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5 months ago
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All questions in this Community
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Not Answered
Download KEIL uVision 4
0
Keil MDK
153207
views
27
replies
Latest
over 6 years ago
by
charishma
Not Answered
Configuration to generate FIQ interrupts on ARMv8
0
16425
views
3
replies
Latest
over 6 years ago
by
Christopher Tory
Answered
ACE MakeUnique Transaction
0
22587
views
2
replies
Latest
over 6 years ago
by
RajaAC
Not Answered
What is the power consumption of a76 gpu and a77 gpu in normal state?
0
Cortex-A77
Cortex-A76
20367
views
0
replies
Started
over 6 years ago
by
Little_lan
Answered
[NIC-400 Interconnect] Remap mode
0
16846
views
2
replies
Latest
over 6 years ago
by
Hieu Ho
Not Answered
Problem with rand_r() and strnlen()
0
4033
views
2
replies
Latest
over 6 years ago
by
Andy Neil
Answered
What can cause getting Cortex-A55 DSU P-Channel PACCEPT/PDENY signals fail?
+1
Cortex-A55
Armv8-A
Cortex-A
25167
views
1
reply
Latest
over 6 years ago
by
Christopher Tory
Answered
MMU attributes implications on memory bandwidth
+1
23720
views
1
reply
Latest
over 6 years ago
by
Christopher Tory
Answered
I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ?
+1
AXI4
16736
views
1
reply
Latest
over 6 years ago
by
Christopher Tory
Answered
Inconsistency in latest AXI4 specification (version g) regarding INCR burst transfers.
+1
AXI4
15836
views
1
reply
Latest
over 6 years ago
by
Christopher Tory
Answered
AMBA 5 CHI Memory Attributes
0
AMBA 5 CHI
15156
views
1
reply
Latest
over 6 years ago
by
Christopher Tory
Answered
Compare the performance of In-order and Out-of-order in AXI protocol
+1
16424
views
1
reply
Latest
over 6 years ago
by
Christopher Tory
Answered
CHI protocol cache line states
+1
AMBA 5 CHI
SoC Verification
19513
views
1
reply
Latest
over 6 years ago
by
Christopher Tory
Answered
Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior
0
AMBA
ACE
ACE 5
interconnect
AMBA 5
31683
views
7
replies
Latest
over 6 years ago
by
Christopher Tory
Suggested Answer
Which ARM cortex M-4/M-3 to buy for development?
0
24602
views
3
replies
Latest
over 6 years ago
by
Andy Neil
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