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MDK Lite V5.35 __main scatterload

Hi  all,

    When I use MDK lite V5.35 I found a problem in _main_scatterload.

   My code is very simple as below:define a arrary which is 9 bytes long。another arrary init to zero.  after build the map file is below.

#define TEST_ADDR1 ((volatile unsigned int*)(0x20020000u))
char test[9]={0,1,2,3,4,5,6,7,8};
//char test1[8]={1,2,3,4,5,6,7,8};
char test1[8]={0};
int main(void)
{
   char ch;
    volatile unsigned int* test_wr = TEST_ADDR1;
   *test_wr = (unsigned int)test1[8];
    test1[6] = test[8];
    while (1)
    {
          test1[7] = test[7];
    }
}

   

in __main, copy data, the length is 9 bytes, R2 is 0x9, every time it subtract 4,then It can never be equal to 0,So it can not run to main() and make a hard fault.

In map file I see it have "3 PAD" , but the copy length is not 0xC, in the .elf is 0x9.

but when the test1 init with non-zero,the map is bellow, and in the .elf file the copy length is 0x14, Is an integer multiple of 4 bytes. So that's No problem.

How to force  "__main" copy length in 4-byte integer multiple ? 

thanks a lot!

Parents
  • I think you had also raised a support case for this. Correct?

    The scatterload functions expect addresses and sizes of the init data to be all 4 bytes aligned. The tools however fail to satisfy this in some situations like in your example.

    This problem should be fixed in the next compiler version. Until then you can use the following workaround:

    Manually force 4 bytes aligned sections in an execution region by using region attribute ALIGN(4). Here en example:

      RW_RAM __RW_BASE ALIGN(4) __RW_SIZE  {                     ; RW data
       .ANY (+RW +ZI)
      }

    (replace __RW_BASE and  __RW_SIZE with your actual values)

Reply
  • I think you had also raised a support case for this. Correct?

    The scatterload functions expect addresses and sizes of the init data to be all 4 bytes aligned. The tools however fail to satisfy this in some situations like in your example.

    This problem should be fixed in the next compiler version. Until then you can use the following workaround:

    Manually force 4 bytes aligned sections in an execution region by using region attribute ALIGN(4). Here en example:

      RW_RAM __RW_BASE ALIGN(4) __RW_SIZE  {                     ; RW data
       .ANY (+RW +ZI)
      }

    (replace __RW_BASE and  __RW_SIZE with your actual values)

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