I can see from the OS Tick API docs that any clock source I use for RTX5 ticking must override the nine weak routines that comprise the API.
My question is then, how do I code up the interrupt handler itself? I'm trying this on an EFM32GG, using the RTC peripheral to replace the Systick used by RTX5 as default.
Can I implement my ISR in C, or does it have to follow the form of RTX5's own SysTick_Handler (in RTX/Source/GCC/irq_cm3.S):
SysTick_Handler: PUSH {R0,LR} // Save EXC_RETURN BL osRtxTick_Handler // Call osRtxTick_Handler POP {R0,LR} // Restore EXC_RETURN MRS R12,PSP B SVC_Context
If I implement my handler in C and just call osRtxTick_Handler, I'd be missing out on the
MRS R12, PSP
B SVC_Context
which I imagine are crucial for correct operation.
I am also unclear how the second parameter to OS_Tick_Setup is used. In RTX5, this function is called by svcRtxKernelStart, passing OS_TICK_HANDLER which is a define for SysTick_Handler? So I have to redefine OS_TICK_HANDLER to be MY isr, i.e. RTC_IRQHandler?
I have been unable to find ANY non-SysTick impl for RTX5 using Cortex-M3, if anyone knows of one, please share.
Stuart
Yes, I understand now, that's a very detailed and informative explanation. I re-coded my RTC IRQ as simply 'B SysTick_Handler' and all is good.